74LVT08PW: 3.3 V Quad 2-input AND gate _ BDTIC 中国领先电子元器件代理商

74LVT08PW: 3.3 V Quad 2-input AND gate

The 74LVT08 is a quad 2-input AND gate. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

74LVT08PW: 产品结构框图

Outline 3d SOT402-1

数据手册 (1)

名称/描述	Modified Date
3.3 V Quad 2-input AND gate (REV 2.0) PDF (87.0 kB) 74LVT08 [English]	29 May 1996

应用说明 (7)

名称/描述	Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]	13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]	13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]	13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]	13 Mar 2013
Test Fixtures for High Speed Logic (REV 1.0) PDF (341.0 kB) AN203 [English]	02 Apr 1998
Transmission Lines and Terminations with Philips Advanced Logic Families (REV 1.0) PDF (217.0 kB) AN246 [English]	01 Feb 1998
LVT (Low Voltage Technology) and ALVT (Advanced LVT) (REV 1.0) PDF (133.0 kB) AN243 [English]	01 Jan 1998

选型工具指南 (2)

名称/描述	Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]	19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]	08 Jan 2015

封装信息 (1)

名称/描述	Modified Date
plastic thin shrink small outline package; 14 leads; body width 4.4 mm (REV 1.0) PDF (285.0 kB) SOT402-1 [English]	08 Feb 2016

包装 (1)

名称/描述	Modified Date
TSSOP14; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 1.0) PDF (217.0 kB) SOT402-1_118 [English]	08 Apr 2013

支持信息 (1)

名称/描述	Modified Date
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]	08 Oct 2009

IBIS

lvt08 IBIS model (REV 1.0) ibs LVT08 4/7/2013

SPICE

lvt Spice model (REV 1.0) ZIP LVT 5/7/2013

订购信息

型号	状态	Family	V_CC (V)	功能	说明	Logic switching levels	类型	Output drive capability (mA)	Package version	t_pd (ns)	f_max (MHz)	No of bits	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74LVT08PW	Active	LVT	2.7 - 3.6	AND gates	quad 2-input AND gate	TTL	AND gates	-32/+64	SOT402-1	3.4	150	4	medium	-40~85	142	8.1	68	TSSOP14	14

封装环保信息

产品编号	封装说明	Outline Version	回流/波峰焊接	包装	产品状态	部件编号订购码 (12NC)	Marking	化学成分	RoHS / 无铅 / RHF	无铅转换日期	EFR	IFR(FIT)	MTBF（小时）	MSL	MSL LF
74LVT08PW		SOT402-1	SSOP-TSSOP-VSO-WAVE	Reel 13" Q1/T1	Active	74LVT08PW,118 (9352 090 40118)	LVT08	74LVT08PW		week 10, 2005	70.8	1.33	7.52E8	1	1
74LVT08PW		SOT402-1	SSOP-TSSOP-VSO-WAVE	Bulk Pack	Active	74LVT08PW,112 (9352 090 40112)	LVT08	74LVT08PW		week 10, 2005	70.8	1.33	7.52E8	1	1