74LVT14DB: 3.3 V十六进制反相器施密特触发器

74LVT14是高性能BiCMOS产品,设计用于3.3 V的VCC操作。它能够将缓慢变化的输入信号转换成清晰无抖动的输出信号。此外,该器件还具有比传统反相器更大的噪声容限。

每个电路都包含一个施密特触发器,后跟一个达林顿电平转换器和一个分相器,可驱动TTL图腾柱极输出。施密特触发器使用正反馈有效加速缓慢的输入转换并针对正向和负向输入提供不同的输入阈值电压。阈值差(通常为600 mV)在内部由电阻比确定,且对温度和电源电压变化不敏感。

74LVT14DB: 产品结构框图
74LVT14DB: 应用结构框图
74LVT14DB: 应用结构框图
74LVT14DB: 应用结构框图
74LVT14DB: 应用结构框图
74LVT14DB: 应用结构框图
Outline 3d SOT337-1
数据手册 (1)
名称/描述Modified Date
3.3 V hex inverter Schmitt trigger (REV 1.0) PDF (90.0 kB) 74LVT14 [English]25 Apr 2008
应用说明 (7)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]13 Mar 2013
Test Fixtures for High Speed Logic (REV 1.0) PDF (341.0 kB) AN203 [English]02 Apr 1998
Transmission Lines and Terminations with Philips Advanced Logic Families (REV 1.0) PDF (217.0 kB) AN246 [English]01 Feb 1998
LVT (Low Voltage Technology) and ALVT (Advanced LVT) (REV 1.0) PDF (133.0 kB) AN243 [English]01 Jan 1998
选型工具指南 (2)
名称/描述Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
封装信息 (1)
名称/描述Modified Date
plastic shrink small outline package; 14 leads; body width 5.3 mm (REV 1.0) PDF (295.0 kB) SOT337-1 [English]08 Feb 2016
包装 (1)
名称/描述Modified Date
Standard product orientation 12NC ending 118 (REV 1.0) PDF (86.0 kB) SOT337-1_118 [English]04 Apr 2013
支持信息 (2)
名称/描述Modified Date
Footprint for reflow soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-REFLOW [English]08 Oct 2009
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]08 Oct 2009
IBIS
SPICE
订购信息
型号状态FamilyVCC (V)功能说明Logic switching levelsPackage versionOutput drive capability (mA)fmax (MHz)tpd (ns)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74LVT14DBActiveLVT2.7 - 3.6Schmitt-triggershex inverter Schmitt-triggerTTLSOT337-1-32/+641503.86medium-40~8515640.0SSOP1414
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期EFRIFR(FIT)MTBF(小时)MSLMSL LF
74LVT14DBSOT337-1SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE
SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE
Reel 13" Q1/T1Active74LVT14DB,118 (9352 091 80118)LVT1474LVT14DBweek 13, 200570.81.337.52E811
Bulk PackActive74LVT14DB,112 (9352 091 80112)LVT1474LVT14DBweek 13, 200570.81.337.52E811
3.3 V hex inverter Schmitt trigger 74LVT14PW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
Ground and VCC Bounce of High-Speed Integrated Circuits 74ALVC164245DGG-Q100
Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100
Test Fixtures for High Speed Logic 74ABTH162245ADL
Transmission Lines and Terminations with Philips Advanced Logic Families 74LVTN16245BDGG
LVT (Low Voltage Technology) and ALVT (Advanced LVT) 74LVTN16245BDGG
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
lvt14 IBIS model 74LVT14PW
lvt Spice model 74LVT640PW
plastic shrink small outline package; 14 leads; body width 5.3 mm 74LVC32A_Q100
Footprint for reflow soldering 74HC_T_595_Q100
SSOP-TSSOP-VSO-WAVE LPC1114FDH28
Standard product orientation 12NC ending 118 74LVC32A_Q100
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