74LVT162373DL: 3.3 V LVT 16位D型透明锁存器,具有30 Ohm端接电阻(3态)

74LVT162373是高性能BiCMOS产品,设计用于3.3 V的VCC操作。

该器件是带非反相3态总线兼容输出的16位穿透D型锁存器。该器件可用作两个8位锁存器或一个16位锁存器。锁存使能(LE)输入为高电平时,Q输出跟随数据(D)输入。锁存使能变为低电平时,Q输出在从高电平跃迁至低电平前的一个设置时间被锁存在D输入的电平。

74LVT162373设计为在输出的高电平和低电平状态中都具有30 Ω串联电阻。这种设计可降低内存地址驱动器、时钟驱动器以及总线接收器/发射器等应用中的噪声。

74LVT162373DL: 产品结构框图
Outline 3d SOT370-1
数据手册 (1)
名称/描述Modified Date
3.3 V LVT 16-bit transparent D-type latch with 30 Ohm termination resistors (3-state) (REV 1.0) PDF (121.0 kB) 74LVT162373 [English]13 Mar 2014
应用说明 (8)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
A metastability primer (REV 1.0) PDF (40.0 kB) AN219 [English]13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]13 Mar 2013
Test Fixtures for High Speed Logic (REV 1.0) PDF (341.0 kB) AN203 [English]02 Apr 1998
Transmission Lines and Terminations with Philips Advanced Logic Families (REV 1.0) PDF (217.0 kB) AN246 [English]01 Feb 1998
LVT (Low Voltage Technology) and ALVT (Advanced LVT) (REV 1.0) PDF (133.0 kB) AN243 [English]01 Jan 1998
选型工具指南 (2)
名称/描述Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
封装信息 (1)
名称/描述Modified Date
plastic shrink small outline package; 48 leads; body width 7.5 mm (REV 1.0) PDF (482.0 kB) SOT370-1 [English]08 Feb 2016
包装 (1)
名称/描述Modified Date
Standard product orientation 12NC ending 118 (REV 2.0) PDF (87.0 kB) SOT370-1_118 [English]19 Apr 2013
支持信息 (2)
名称/描述Modified Date
Footprint for reflow soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-REFLOW [English]08 Oct 2009
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]08 Oct 2009
IBIS
订购信息
型号状态Family功能VCC (V)说明Logic switching levelsOutput drive capability (mA)Package versiontpd (ns)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74LVT162373DLActiveLVTLatches/registered drivers2.7 - 3.616-bit D-type transparent latch with bus hold and 30 ohm termination resistors (3-state)TTL+/- 12SOT370-12.516medium-40~858825.0SSOP4848
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期EFRIFR(FIT)MTBF(小时)MSLMSL LF
74LVT162373DLSOT370-1SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE
SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE
Reel 13" Q1/T1Active74LVT162373DL,118 (9352 641 63118)LVT16237374LVT162373DLweek 13, 200570.81.337.52E811
Bulk PackActive74LVT162373DL,112 (9352 641 63112)LVT16237374LVT162373DLweek 13, 200570.81.337.52E811
3.3 V LVT 16-bit transparent D-type latch with 30 Ohm termination resistors (3-state) 74LVT162373DL
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
A metastability primer 74AHC573PW
Ground and VCC Bounce of High-Speed Integrated Circuits 74ALVC164245DGG-Q100
Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100
Test Fixtures for High Speed Logic 74ABTH162245ADL
Transmission Lines and Terminations with Philips Advanced Logic Families 74LVTN16245BDGG
LVT (Low Voltage Technology) and ALVT (Advanced LVT) 74LVTN16245BDGG
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
lvt162373 IBIS model 74LVT162373DL
plastic shrink small outline package; 48 leads; body width 7.5 mm gtl2000dl
Footprint for reflow soldering 74HC_T_595_Q100
SSOP-TSSOP-VSO-WAVE LPC1114FDH28
Standard product orientation 12NC ending 118 gtl2000dl
74LVT16373A
74LVT162245B