74LVT16543ADGG: 3.3V LVT 16位寄存收发器(3态)

74LVT16543A是高性能BiCMOS产品,设计用于3.3 V的Vcc操作。该器件可用作两个8位收发器或一个16位收发器。

74LVT16543A包含两组八位元D型锁存器,每组都具有单独的控制针脚。以A到B的数据流为例, A到B使能(nEAB)输入和A到B锁存使能(nLEAB)输入为低电平时,A到B路径是透明的。

nLEAB信号后续的低电平至高电平跃迁会将A数据置入存储其的锁存器中,且B输出不再随A输入变化。nEAB和nOEAB都为低电平时,3态B输出缓冲器处于激活状态并且会显示A锁存器输出处存在的数据。

控制B到A的数据流类似,不过其使用的是nEBA、nLEBA和nOEBA输入。

提供有源总线保持电路是为了使闲置或浮动数据输入保持在有效逻辑电平。

74LVT16543ADGG: 产品结构框图
Outline 3d SOT364-1
数据手册 (1)
名称/描述Modified Date
3.3 V LVT 16-bit registered transceiver (3-state) (REV 2.0) PDF (94.0 kB) 74LVT16543A [English]13 Mar 2014
应用说明 (7)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]13 Mar 2013
Test Fixtures for High Speed Logic (REV 1.0) PDF (341.0 kB) AN203 [English]02 Apr 1998
Transmission Lines and Terminations with Philips Advanced Logic Families (REV 1.0) PDF (217.0 kB) AN246 [English]01 Feb 1998
LVT (Low Voltage Technology) and ALVT (Advanced LVT) (REV 1.0) PDF (133.0 kB) AN243 [English]01 Jan 1998
选型工具指南 (2)
名称/描述Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
封装信息 (1)
名称/描述Modified Date
plastic thin shrink small outline package; 56 leads; body width 6.1 mm (REV 1.0) PDF (506.0 kB) SOT364-1 [English]08 Feb 2016
包装 (1)
名称/描述Modified Date
TSSOP56; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 4.0) PDF (248.0 kB) SOT364-1_118 [English]15 Apr 2013
支持信息 (1)
名称/描述Modified Date
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]08 Oct 2009
IBIS
SPICE
订购信息
型号状态FamilyVCC (V)功能说明Logic switching levelsPackage versionOutput drive capabilitytpd (ns)No of bitsfmax (MHz)Power dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74LVT16543ADGGActiveLVT2.7 - 3.6Transceivers16-bit registered transceiver with bus hold (3-state)TTLSOT364-1-32/+642.216150medium9321.0TSSOP5656
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期EFRIFR(FIT)MTBF(小时)MSLMSL LF
74LVT16543ADGGSOT364-1SSOP-TSSOP-VSO-WAVETube in DrypackActive74LVT16543ADGGS (9352 030 40512)LVT16543A74LVT16543ADGGAlways Pb-free70.81.337.52E811
Reel 13" Q1/T1 in DrypackActive74LVT16543ADGGY (9352 030 40518)LVT16543A74LVT16543ADGGAlways Pb-free70.81.337.52E811
Bulk PackDiscontinued74LVT16543ADGG,112 (9352 030 40112)LVT16543A74LVT16543ADGGweek 2, 200670.81.337.52E811
Reel 13" Q1/T1Withdrawn74LVT16543ADGG,118 (9352 030 40118)LVT16543A74LVT16543ADGGweek 2, 200670.81.337.52E811
3.3 V LVT 16-bit registered transceiver (3-state) 74LVT16543ADL
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
Ground and VCC Bounce of High-Speed Integrated Circuits 74ALVC164245DGG-Q100
Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100
Test Fixtures for High Speed Logic 74ABTH162245ADL
Transmission Lines and Terminations with Philips Advanced Logic Families 74LVTN16245BDGG
LVT (Low Voltage Technology) and ALVT (Advanced LVT) 74LVTN16245BDGG
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
lvt16543a IBIS model 74LVT16543ADL
lvt16 Spice model 74LVT16543ADL
plastic thin shrink small outline package; 56 leads; body width 6.1 mm pcf8576d_automotive
SSOP-TSSOP-VSO-WAVE LPC1114FDH28
TSSOP56; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... pcf8576d_automotive
74LVT16543A
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