UPD70F3796F1-CAH-A

DataSheet 数据书册
下载文件
UPD70F3796F1-CAH-A.pdf
相关开发工具
型号厂家状态
R0E000200KCT00RenesasMassProduction
R0E000010KCE00RenesasMassProduction
Basic Information
Product StatusNon-promotion
FamilyV850
SeriesV850ES/Jx
GroupV850ES/Jx3-L(USB)

Memory
Program memory512 KB Flash memory
RAM40 KB

CPU (Bit, Clock, DMA, External Bus etc)
CPUV850ES (32-bit)
Max. Frequency20 MHz
Sub-Clock (32.768 kHz)YES
On-chip Oscillator Freq.Low Speed:220kHz
PLLYES
Real-Time Clock (RTC)YES
Low Voltage DetectionYES
DMA RemarksDMAC x 4 ch
External Address/Data BusYES
External Interrupt Pins9
I/O Ports80

Timers
16-bit Timers8 ch
Watchdog Timers1 ch
Other TimersWatch Timer x 1 ch
PWM Output7

Analog
A/D Converters10-bit x 12 ch
D/A Converters8-bit x 2 ch

Interfaces
USB Ports1
USB PeripheralYES
USB RemarksMain clock = 16MHz when USB is used. Provides free sample code for USB CDC, HID, Mass Storage class.
CSIs5 ch
UARTs7 ch
I2Cs3 ch
LIN7 ch

Operating Conditions
Operating Voltage2 to 3.6 V
Power Supply3.0 V to 3.6 V (USB operating)
Operating Temperature-40 to 85 ℃ (Ambient Temperature)

Remarks
Remarks32-bit microcontroller with USBF (V850ES/JG3-L: Flash 512 KB, RAM 40 KB, 20MHz, 121-pin FBGA)

Package
Pins121
Terminal pitch (mm)0.65 mm
Package TypeLFBGA
Dimensions (mm)8x8 mm2
Drawing Linkp121f1-65-cah
Mount padfig0013e
Mounting height (mm)[MAX]1.31 mm
Mass (g) [TYP,]0.15 g
Renesas codePLBG0121JA-A (old: P121F1-65-CAH-1 )
JEITA codeP-LFBGA121-8x8-0.65
RemarksB-FPBGA
Terminal material - BaseSn-Ag-Cu
Terminal material - Surface-
订购型号
型号状态产品长期供应计划预算价格(1000片) 包装明星产品RoHS
UPD70F3796F1-CAH-ANon-promotionJan, 2024-| MOQ:| WRAP_SPEC:-| OTHER_ENV:false无铅
UPD70F3796F1(S)-CAH-ANon-promotionJan, 2024| MOQ:| WRAP_SPEC:| OTHER_ENV:false无铅
UPD70F3796F1(R)-CAH-ANon-promotionJan, 2024| MOQ:| WRAP_SPEC:| OTHER_ENV:false无铅
V850ES/JG3-L (on-chip USB controller) architecture Preliminary User's Manual Hardware Aug.01.10;Rev.0.01;12.04 Mbytes
V850ES/JG3-L (on-chip USB controller) User's Manual: Hardware Mar.25.14;Rev.4.00;7.4 Mbytes