cpldfit: version H.38 Xilinx Inc. No Fit Report Design Name: walkthru1_top Date: 3-16-2005, 12:59PM Device Used: XC2C32A-4-PC44 Fitting Status: Design Rule Checking Failed ************************** Errors and Warnings *************************** ERROR:Cpld:1063 - Design requires at least 34 macrocells, exceeds device limit 32. ERROR:Cpld:1064 - Design rules checking error. Fitting process stopped. ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with the selected implementation options. ************************* Mapped Resource Summary ************************** No logic has been mapped. Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 0 /32 ( 0%) 0 /112 ( 0%) 0 /80 ( 0%) 0 /32 ( 0%) 0 /33 ( 0%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO CTC CTR CTS CTE Block Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot FB1 0/16 0/40 0/56 0/16 0/1 0/1 0/1 0/1 FB2 0/16 0/40 0/56 0/16 0/1 0/1 0/1 0/1 ----- ------- ------- ----- --- --- --- --- Total 0/32 0/80 0/112 0/32 0/2 0/2 0/2 0/2 CTC - Control Term Clock CTR - Control Term Reset CTS - Control Term Set CTE - Control Term Output Enable * - Resource is exhausted ** Global Control Resources ** GCK GSR GTS Used/Tot Used/Tot Used/Tot 0/3 0/1 0/4 ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ | I : 0 1 Input : 5 0 | I/O : 0 24 Output : 2 0 | GCK/IO : 0 3 Bidirectional : 0 0 | GTS/IO : 0 4 GCK : 0 0 | GSR/IO : 0 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 7 0 End of Mapped Resource Summary ************************* Summary of UnMapped Logic ************************ ** 2 Outputs ** Signal Total Total I/O User Name Pts Inps STD Assignment o1 1 29 LVCMOS18 o2 1 31 LVCMOS18 ** 32 Buried Nodes ** Signal Total Total User Name Pts Inps Assignment N_PZ_275 2 5 N_PZ_278 1 3 q<0> 3 5 q<1> 3 6 q<2> 3 7 q<3> 3 8 q<4> 3 9 q<5> 3 10 q<6> 3 11 q<7> 3 12 q<8> 3 11 q<9> 3 12 q<10> 3 13 q<11> 3 14 q<12> 3 15 q<13> 3 16 q<14> 3 17 q<15> 3 18 q<16> 3 19 q<17> 3 20 q<18> 3 21 q<19> 3 22 q<20> 3 23 q<21> 3 24 q<22> 3 25 q<23> 3 26 q<24> 3 27 q<25> 3 28 q<26> 3 29 q<27> 3 30 q<28> 3 31 q<29> 3 32 ** 5 Inputs ** Signal I/O User Name STD Assignment clk LVCMOS18 en1 LVCMOS18 en2 LVCMOS18 en3 LVCMOS18 reset LVCMOS18 ******************************* Equations ******************************** ********** UnMapped Logic ********** ** Outputs ** o1 <= (en3 AND en2 AND en1 AND NOT q(0) AND NOT q(10) AND NOT q(1) AND NOT q(4) AND q(5) AND q(6) AND NOT q(11) AND NOT q(12) AND NOT q(13) AND NOT q(14) AND NOT q(15) AND NOT q(16) AND NOT q(17) AND NOT q(18) AND NOT q(19) AND NOT q(20) AND NOT q(21) AND NOT q(22) AND NOT q(23) AND NOT q(24) AND NOT q(25) AND NOT q(26) AND NOT q(27) AND NOT q(28) AND NOT q(29) AND N_PZ_275); o2 <= (en3 AND en2 AND en1 AND NOT q(0) AND NOT q(10) AND NOT q(2) AND NOT q(1) AND q(3) AND q(8) AND NOT q(4) AND N_PZ_278 AND q(9) AND NOT q(11) AND NOT q(12) AND NOT q(13) AND NOT q(14) AND NOT q(15) AND NOT q(16) AND NOT q(17) AND NOT q(18) AND NOT q(19) AND NOT q(20) AND NOT q(21) AND NOT q(22) AND NOT q(23) AND NOT q(24) AND NOT q(25) AND NOT q(26) AND NOT q(27) AND NOT q(28) AND NOT q(29)); ** Buried Nodes ** N_PZ_275 <= ((q(2) AND NOT q(3) AND NOT q(8) AND NOT q(7) AND NOT q(9)) OR (NOT q(2) AND q(3) AND q(8) AND q(7) AND q(9))); N_PZ_278 <= (q(7) AND q(5) AND q(6)); FTCPE_q0: FTCPE port map (q(0),q_T(0),clk,reset,'0','1'); q_T(0) <= (en3 AND en2 AND en1); FTCPE_q1: FTCPE port map (q(1),q_T(1),clk,reset,'0','1'); q_T(1) <= (en3 AND en2 AND en1 AND q(0)); FTCPE_q2: FTCPE port map (q(2),q_T(2),clk,reset,'0','1'); q_T(2) <= (en3 AND en2 AND en1 AND q(0) AND q(1)); FTCPE_q3: FTCPE port map (q(3),q_T(3),clk,reset,'0','1'); q_T(3) <= (en3 AND en2 AND en1 AND q(0) AND q(2) AND q(1)); FTCPE_q4: FTCPE port map (q(4),q_T(4),clk,reset,'0','1'); q_T(4) <= (en3 AND en2 AND en1 AND q(0) AND q(2) AND q(1) AND q(3)); FTCPE_q5: FTCPE port map (q(5),q_T(5),clk,reset,'0','1'); q_T(5) <= (en3 AND en2 AND en1 AND q(0) AND q(2) AND q(1) AND q(3) AND q(4)); FTCPE_q6: FTCPE port map (q(6),q_T(6),clk,reset,'0','1'); q_T(6) <= (en3 AND en2 AND en1 AND q(0) AND q(2) AND q(1) AND q(3) AND q(4) AND q(5)); FTCPE_q7: FTCPE port map (q(7),q_T(7),clk,reset,'0','1'); q_T(7) <= (en3 AND en2 AND en1 AND q(0) AND q(2) AND q(1) AND q(3) AND q(4) AND q(5) AND q(6)); FTCPE_q8: FTCPE port map (q(8),q_T(8),clk,reset,'0','1'); q_T(8) <= (en3 AND en2 AND en1 AND q(0) AND q(2) AND q(1) AND q(3) AND q(4) AND N_PZ_278); FTCPE_q9: FTCPE port map (q(9),q_T(9),clk,reset,'0','1'); q_T(9) <= (en3 AND en2 AND en1 AND q(0) AND q(2) AND q(1) AND q(3) AND q(8) AND q(4) AND N_PZ_278); FTCPE_q10: FTCPE port map (q(10),q_T(10),clk,reset,'0','1'); q_T(10) <= (en3 AND en2 AND en1 AND q(0) AND q(2) AND q(1) AND q(3) AND q(8) AND q(4) AND N_PZ_278 AND q(9)); FTCPE_q11: FTCPE port map (q(11),q_T(11),clk,reset,'0','1'); q_T(11) <= (en3 AND en2 AND en1 AND q(0) AND q(10) AND q(2) AND q(1) AND q(3) AND q(8) AND q(4) AND N_PZ_278 AND q(9)); FTCPE_q12: FTCPE port map (q(12),q_T(12),clk,reset,'0','1'); q_T(12) <= (en3 AND en2 AND en1 AND q(0) AND q(10) AND q(2) AND q(1) AND q(3) AND q(8) AND q(4) AND N_PZ_278 AND q(9) AND q(11)); FTCPE_q13: FTCPE port map (q(13),q_T(13),clk,reset,'0','1'); q_T(13) <= (en3 AND en2 AND en1 AND q(0) AND q(10) AND q(2) AND q(1) AND q(3) AND q(8) AND q(4) AND N_PZ_278 AND q(9) AND q(11) AND q(12)); FTCPE_q14: FTCPE port map (q(14),q_T(14),clk,reset,'0','1'); q_T(14) <= (en3 AND en2 AND en1 AND q(0) AND q(10) AND q(2) AND q(1) AND q(3) AND q(8) AND q(4) AND N_PZ_278 AND q(9) AND q(11) AND q(12) AND q(13)); FTCPE_q15: FTCPE port map (q(15),q_T(15),clk,reset,'0','1'); q_T(15) <= (en3 AND en2 AND en1 AND q(0) AND q(10) AND q(2) AND q(1) AND q(3) AND q(8) AND q(4) AND N_PZ_278 AND q(9) AND q(11) AND q(12) AND q(13) AND q(14)); FTCPE_q16: FTCPE port map (q(16),q_T(16),clk,reset,'0','1'); q_T(16) <= (en3 AND en2 AND en1 AND q(0) AND q(10) AND q(2) AND q(1) AND q(3) AND q(8) AND q(4) AND N_PZ_278 AND q(9) AND q(11) AND q(12) AND q(13) AND q(14) AND q(15)); FTCPE_q17: FTCPE port map (q(17),q_T(17),clk,reset,'0','1'); q_T(17) <= (en3 AND en2 AND en1 AND q(0) AND q(10) AND q(2) AND q(1) AND q(3) AND q(8) AND q(4) AND N_PZ_278 AND q(9) AND q(11) AND q(12) AND q(13) AND q(14) AND q(15) AND q(16)); FTCPE_q18: FTCPE port map (q(18),q_T(18),clk,reset,'0','1'); q_T(18) <= (en3 AND en2 AND en1 AND q(0) AND q(10) AND q(2) AND q(1) AND q(3) AND q(8) AND q(4) AND N_PZ_278 AND q(9) AND q(11) AND q(12) AND q(13) AND q(14) AND q(15) AND q(16) AND q(17)); FTCPE_q19: FTCPE port map (q(19),q_T(19),clk,reset,'0','1'); q_T(19) <= (en3 AND en2 AND en1 AND q(0) AND q(10) AND q(2) AND q(1) AND q(3) AND q(8) AND q(4) AND N_PZ_278 AND q(9) AND q(11) AND q(12) AND q(13) AND q(14) AND q(15) AND q(16) AND q(17) AND q(18)); FTCPE_q20: FTCPE port map (q(20),q_T(20),clk,reset,'0','1'); q_T(20) <= (en3 AND en2 AND en1 AND q(0) AND q(10) AND q(2) AND q(1) AND q(3) AND q(8) AND q(4) AND N_PZ_278 AND q(9) AND q(11) AND q(12) AND q(13) AND q(14) AND q(15) AND q(16) AND q(17) AND q(18) AND q(19)); FTCPE_q21: FTCPE port map (q(21),q_T(21),clk,reset,'0','1'); q_T(21) <= (en3 AND en2 AND en1 AND q(0) AND q(10) AND q(2) AND q(1) AND q(3) AND q(8) AND q(4) AND N_PZ_278 AND q(9) AND q(11) AND q(12) AND q(13) AND q(14) AND q(15) AND q(16) AND q(17) AND q(18) AND q(19) AND q(20)); FTCPE_q22: FTCPE port map (q(22),q_T(22),clk,reset,'0','1'); q_T(22) <= (en3 AND en2 AND en1 AND q(0) AND q(10) AND q(2) AND q(1) AND q(3) AND q(8) AND q(4) AND N_PZ_278 AND q(9) AND q(11) AND q(12) AND q(13) AND q(14) AND q(15) AND q(16) AND q(17) AND q(18) AND q(19) AND q(20) AND q(21)); FTCPE_q23: FTCPE port map (q(23),q_T(23),clk,reset,'0','1'); q_T(23) <= (en3 AND en2 AND en1 AND q(0) AND q(10) AND q(2) AND q(1) AND q(3) AND q(8) AND q(4) AND N_PZ_278 AND q(9) AND q(11) AND q(12) AND q(13) AND q(14) AND q(15) AND q(16) AND q(17) AND q(18) AND q(19) AND q(20) AND q(21) AND q(22)); FTCPE_q24: FTCPE port map (q(24),q_T(24),clk,reset,'0','1'); q_T(24) <= (en3 AND en2 AND en1 AND q(0) AND q(10) AND q(2) AND q(1) AND q(3) AND q(8) AND q(4) AND N_PZ_278 AND q(9) AND q(11) AND q(12) AND q(13) AND q(14) AND q(15) AND q(16) AND q(17) AND q(18) AND q(19) AND q(20) AND q(21) AND q(22) AND q(23)); FTCPE_q25: FTCPE port map (q(25),q_T(25),clk,reset,'0','1'); q_T(25) <= (en3 AND en2 AND en1 AND q(0) AND q(10) AND q(2) AND q(1) AND q(3) AND q(8) AND q(4) AND N_PZ_278 AND q(9) AND q(11) AND q(12) AND q(13) AND q(14) AND q(15) AND q(16) AND q(17) AND q(18) AND q(19) AND q(20) AND q(21) AND q(22) AND q(23) AND q(24)); FTCPE_q26: FTCPE port map (q(26),q_T(26),clk,reset,'0','1'); q_T(26) <= (en3 AND en2 AND en1 AND q(0) AND q(10) AND q(2) AND q(1) AND q(3) AND q(8) AND q(4) AND N_PZ_278 AND q(9) AND q(11) AND q(12) AND q(13) AND q(14) AND q(15) AND q(16) AND q(17) AND q(18) AND q(19) AND q(20) AND q(21) AND q(22) AND q(23) AND q(24) AND q(25)); FTCPE_q27: FTCPE port map (q(27),q_T(27),clk,reset,'0','1'); q_T(27) <= (en3 AND en2 AND en1 AND q(0) AND q(10) AND q(2) AND q(1) AND q(3) AND q(8) AND q(4) AND N_PZ_278 AND q(9) AND q(11) AND q(12) AND q(13) AND q(14) AND q(15) AND q(16) AND q(17) AND q(18) AND q(19) AND q(20) AND q(21) AND q(22) AND q(23) AND q(24) AND q(25) AND q(26)); FTCPE_q28: FTCPE port map (q(28),q_T(28),clk,reset,'0','1'); q_T(28) <= (en3 AND en2 AND en1 AND q(0) AND q(10) AND q(2) AND q(1) AND q(3) AND q(8) AND q(4) AND N_PZ_278 AND q(9) AND q(11) AND q(12) AND q(13) AND q(14) AND q(15) AND q(16) AND q(17) AND q(18) AND q(19) AND q(20) AND q(21) AND q(22) AND q(23) AND q(24) AND q(25) AND q(26) AND q(27)); FTCPE_q29: FTCPE port map (q(29),q_T(29),clk,reset,'0','1'); q_T(29) <= (en3 AND en2 AND en1 AND q(0) AND q(10) AND q(2) AND q(1) AND q(3) AND q(8) AND q(4) AND N_PZ_278 AND q(9) AND q(11) AND q(12) AND q(13) AND q(14) AND q(15) AND q(16) AND q(17) AND q(18) AND q(19) AND q(20) AND q(21) AND q(22) AND q(23) AND q(24) AND q(25) AND q(26) AND q(27) AND q(28)); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FDDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); FTDCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc2c32a-4-PC44 Optimization Method : DENSITY Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Set Unused I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Enable Input Registers : ON Function Block Fan-in Limit : 38 Use DATA_GATE Attribute : ON Set Tristate Outputs to Termination Mode : KEEPER Default Voltage Standard for All Outputs : LVCMOS18 Input Limit : 32 Pterm Limit : 28