Failure Table

Signal Name FB1 FB2
N_PZ_275 unk unk
N_PZ_278 unk unk
o1 unk unk
o2 unk unk
q<0> unk unk
q<10> unk unk
q<11> unk unk
q<12> unk unk
q<13> unk unk
q<14> unk unk
q<15> unk unk
q<16> unk unk
q<17> unk unk
q<18> unk unk
q<19> unk unk
q<1> unk unk
q<20> unk unk
q<21> unk unk
q<22> unk unk
q<23> unk unk
q<24> unk unk
q<25> unk unk
q<26> unk unk
q<27> unk unk
q<28> unk unk
q<29> unk unk
q<2> unk unk
q<3> unk unk
q<4> unk unk
q<5> unk unk
q<6> unk unk
q<7> unk unk
q<8> unk unk
q<9> unk unk
Legend:
bnk - signal is assigned to a different I/O bank than this FB
ce - signal clock enable cannot be placed
clk - signal clock cannot be placed
fbi - insufficient function block inputs available to place signal
io - insufficient I/O pins available to place output
loc - signal cannot be placed in this FB because it is assigned to a different FB
mc - insufficient macrocells available to place signal
pt - insufficient product terms available to place signal
sr - signal set/reset cannot be placed
unk - unknown reason for failure - Please contact Xilinx Support