483TEST2 Project Status | |||
Project File: | 483test2.ise | Current State: | Programming File Generated |
Module Name: | module_schem |
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No Errors |
Target Device: | xc3s500e-4fg320 |
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2 Warnings |
Product Version: | ISE 9.1.03i |
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Wed Apr 11 09:37:01 2007 |
Device Utilization Summary | ||||
Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Flip Flops | 97 | 9,312 | 1% | |
Number of 4 input LUTs | 106 | 9,312 | 1% | |
Logic Distribution | ||||
Number of occupied Slices | 111 | 4,656 | 2% | |
Number of Slices containing only related logic | 111 | 111 | 100% | |
Number of Slices containing unrelated logic | 0 | 111 | 0% | |
Total Number of 4 input LUTs | 196 | 9,312 | 2% | |
Number used as logic | 106 | |||
Number used as a route-thru | 90 | |||
Number of bonded IOBs | 23 | 232 | 9% | |
Number of GCLKs | 1 | 24 | 4% | |
Total equivalent gate count for design | 2,030 | |||
Additional JTAG gate count for IOBs | 1,104 |
Performance Summary | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
Timing Constraints: | All Constraints Met |
Detailed Reports | |||||
Report Name | Status | Generated | Errors | Warnings | Infos |
Synthesis Report | Current | Wed Apr 11 09:27:25 2007 | 0 | 2 Warnings | 1 Info |
Translation Report | Current | Wed Apr 11 09:36:06 2007 | 0 | 0 | 0 |
Map Report | Current | Wed Apr 11 09:36:21 2007 | 0 | 0 | 3 Infos |
Place and Route Report | Current | Wed Apr 11 09:36:40 2007 | 0 | 0 | 2 Infos |
Static Timing Report | Current | Wed Apr 11 09:36:47 2007 | 0 | 0 | 3 Infos |
Bitgen Report | Current | Wed Apr 11 09:37:00 2007 | 0 | 0 | 0 |
Secondary Reports | ||
Report Name | Status | Generated |
Xplorer Report |