483TEST2 Project Status
Project File: 483test2.ise Current State: Programming File Generated
Module Name: module_schem
  • Errors:
No Errors
Target Device: xc3s500e-4fg320
  • Warnings:
2 Warnings
Product Version: ISE 9.1.03i
  • Updated:
Wed Apr 11 09:37:01 2007
 
Device Utilization Summary
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 97 9,312 1%  
Number of 4 input LUTs 106 9,312 1%  
Logic Distribution     
Number of occupied Slices 111 4,656 2%  
    Number of Slices containing only related logic 111 111 100%  
    Number of Slices containing unrelated logic 0 111 0%  
Total Number of 4 input LUTs 196 9,312 2%  
Number used as logic 106      
Number used as a route-thru 90      
Number of bonded IOBs 23 232 9%  
Number of GCLKs 1 24 4%  
Total equivalent gate count for design 2,030      
Additional JTAG gate count for IOBs 1,104      
 
Performance Summary
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Apr 11 09:27:25 200702 Warnings1 Info
Translation ReportCurrentWed Apr 11 09:36:06 2007000
Map ReportCurrentWed Apr 11 09:36:21 2007003 Infos
Place and Route ReportCurrentWed Apr 11 09:36:40 2007002 Infos
Static Timing ReportCurrentWed Apr 11 09:36:47 2007003 Infos
Bitgen ReportCurrentWed Apr 11 09:37:00 2007000
 
Secondary Reports
Report NameStatusGenerated
Xplorer Report