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ADF4252 Lowest Phase Noise PLL Synthesizer using Fractional-N Technology

The ADF4252 is a dual fractional-N/integer-N frequency synthesizer that can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters. Both the RF and IF synthesizers consist of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. The RF synthesizer has a Σ-Δ-based fractional interpolator that allows programmable fractional-N division. The IF synthesizer has programmable integer-N counters. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). Applications Base stations for mobile radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs Communications test equipment CATV equipment

Control of all the on-chip registers is via a simple 3-wire interface. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use.

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Frequently Asked Questions

Order Information

Evaluation Boards

Reference Materials

• Product Selection Guide：RF Source Booklet
• Technical Articles：Phase Locked Loops for High-Frequency Receivers and Transmitters – Part 1
• Technical Articles：Phase-Locked Loops for High-Frequency Receivers and Transmitters - Part 2
• Technical Articles：Phase Locked Loops for High-Frequency Receivers and Transmitters – Part 3