Provides Low-Cost, World-Class Secure Authentication of Peripherals and Systems
The DS28E01-100 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write operations. All memory pages can be write protected, and one page can be put in EPROM-emulation mode, where bits can only be changed from a 1 to a 0 state. Each DS28E01-100 has its own guaranteed unique 64-bit ROM registration number that is factory lasered into the chip. The DS28E01-100 communicates over the single-contact 1-Wire® bus. The communication follows the standard 1-Wire protocol with the registration number acting as the node address in the case of a multidevice 1-Wire network.
Key Features
| Applications/Uses
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| title | Download file |
|---|---|
| DS28E01-100 Data Sheet | DS28E01-100.pdf |
| Part Number | Applications | Memory Type | Memory Size | Bus Type | VSUPPLY (V) | Oper. Temp. (°C) | Package/Pins |
|---|---|---|---|---|---|---|---|
| DS28E01-100 | Rack Card Security | EEPROM | 1K x 1 | 1-Wire | 2.8 to 5.25 | -40 to +85 | SFN/2 TDFN-EP/6 TO92/2 TSOC/6 |
| Part Number | Status | Recommended Replacement | Package | Temp | RoHS |
|---|---|---|---|---|---|
| DS28E01-100+ | Active | TO92,;2 pin;19.5 mm² | -40°C to +85°C | Lead Free | |
| DS28E01G-100+T&R | Active | SFN,;2 pin;37.2 mm² | -40°C to +85°C | Lead Free | |
| DS28E01G-100+U | Active | SFN,;2 pin;37.2 mm² | -40°C to +85°C | Lead Free | |
| DS28E01P-100+ | Active | TSOC,;6 pin;17.8 mm² | -40°C to +85°C | Lead Free | |
| DS28E01P-100+T | Active | TSOC,;6 pin;17.8 mm² | -40°C to +85°C | Lead Free | |
| DS28E01Q-100+T&R | Active | TDFN-EP,;6 pin;9.6 mm² | -40°C to +85°C | Lead Free | |
| DS28E01Q-100+U | Active | TDFN-EP,;6 pin;9.6 mm² | -40°C to +85°C | Lead Free |
