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MAX9160：LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver

The MAX9160 125MHz, 14-port LVTTL/LVCMOS clock driver repeats the selected LVDS or LVTTL/LVCMOS input on two output banks. Each bank consists of seven LVTTL/LVCMOS series terminated outputs and a bank enable. The LVDS input has a fail-safe function. The MAX9160 has a propagation delay that can be adjusted using an external resistor to set the bias current for an internal delay cell. The LVTTL/LVCMOS outputs feature 200ps maximum output-to-output skew and ±100ps maximum added peak-to-peak jitter. The MAX9160 is designed to operate with a 3.3V supply voltage over the extended temperature range of -40°C to +85°C. This device is available in 28-pin exposed- and nonexposed-pad TSSOP and 32-lead 5mm x 5mm QFN packages.

Key Features LVDS or LVTTL/LVCMOS Input Selection LVDS Input Fail-Safe Sets Outputs High for Open, Undriven Short, or Undriven Parallel Termination Two Output Banks with Separate Bank Enables Integrated Output Series Termination for 60Ω Lines 200ps (max) Output-to-Output Skew ±100ps (max) Peak-to-Peak Added Output Jitter 42% to 58% Output Duty Cycle at 125MHz Guaranteed 125MHz Operating Frequency LVDS Input Is High Impedance with VCC = 0V or Open (Hot Swappable) 28-Pin Exposed- and Nonexposed-Pad TSSOP or 32-Lead QFN Packages -40°C to +85°C Operating Temperature 3.0V to 3.6V Supply Voltage

MAX9160: Typical Operating Circuit Applications/Uses Add/Drop Multiplexers Cell Phone Base Stations Digital Cross-Connects DSLAM Network Equipment Servers

DataSheet

Parametrics

Quality and Environmental Data

• MAX9160.pdf

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