74AHC273BQ: Octal D-type flip-flop with reset; positive-edge trigger

The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.

The 74AHC273; 74AHCT273 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs.

The common clock (CP) and master reset (MR) inputs, load and reset (clear) all flip-flops simultaneously.

The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop.

All outputs will be forced LOW, independent of clock or data inputs, by a LOW on the MR input.

The device is useful for applications where only the true output is required and the clock and master reset are common to all storage elements.

74AHC273BQ: Product Block Diagram
Outline 3d SOT764-1
Data Sheets (1)
Name/DescriptionModified Date
Octal D-type flip-flop with reset; positive-edge trigger (REV 3.0) PDF (104.0 kB) 74AHC_AHCT273 [English]13 May 2008
Application Notes (5)
Name/DescriptionModified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]13 Mar 2013
Pin FMEA for AHC/AHCT family (REV 1.0) PDF (52.0 kB) AN11106 [English]04 Nov 2011
Brochures (2)
Name/DescriptionModified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
Package Information (1)
Name/DescriptionModified Date
plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x... (REV 1.0) PDF (190.0 kB) SOT764-1 [English]08 Feb 2016
Packing (1)
Name/DescriptionModified Date
DHVQFN20; Reel pack; SMD, 7" Q1/T1 Standard product orientation Orderable part number ending ,115 or... (REV 4.0) PDF (203.0 kB) SOT764-1_115 [English]23 Apr 2013
IBIS Model
Ordering Information
ProductStatusFamilyVCC (V)FunctionLogic switching levelsDescriptionOutput drive capability (mA)Package versiontpd (ns)fmax (MHz)Power dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AHC273BQActiveAHC(T)2.0 - 5.5D-type flip-flopsCMOSpositive-edge trigger+/- 8SOT764-14.2165low-40~125789.150DHVQFN2020
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateEFRIFR(FIT)MTBF(hour)MSLMSL LF
74AHC273BQSOT764-1Reel 7" Q1/T1Active74AHC273BQ,115 (9352 730 49115)AHC27374AHC273BQAlways Pb-free84.96.621.51E811
Octal D-type flip-flop with reset; positive-edge trigger 74AHCT273PW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
Ground and VCC Bounce of High-Speed Integrated Circuits 74ALVC164245DGG-Q100
Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100
Pin FMEA for AHC/AHCT family 74AHC_T_245_Q100
電圧レベルシフタ 74AVC16245DGG-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ahc273 IBIS model 74AHC273PW
plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x... 74LVC_H_245A_Q100
DHVQFN20; Reel pack; SMD, 7" Q1/T1 Standard product orientation Orderable part number ending ,115 or... 74LVC_H_245A_Q100
74HC_T_273
74VHC_T_245