74ALVC00PW: Quad 2-input NAND gate _ BDTIC a Leading Distributor in China

74ALVC00PW: Quad 2-input NAND gate

The 74ALVC00 is a quad 2-input NAND gate.

Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times.

74ALVC00PW: Product Block Diagram

Outline 3d SOT402-1

Data Sheets (1)

Name/Description	Modified Date
Quad 2-input NAND gate (REV 3.0) PDF (181.0 kB) 74ALVC00 [English]	16 May 2014

Application Notes (4)

Name/Description	Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]	13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]	13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]	13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]	13 Mar 2013

Brochures (2)

Name/Description	Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]	16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]	20 May 2014

Selector Guides (2)

Name/Description	Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]	19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]	08 Jan 2015

Package Information (1)

Name/Description	Modified Date
plastic thin shrink small outline package; 14 leads; body width 4.4 mm (REV 1.0) PDF (285.0 kB) SOT402-1 [English]	08 Feb 2016

Packing (1)

Name/Description	Modified Date
TSSOP14; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 1.0) PDF (217.0 kB) SOT402-1_118 [English]	08 Apr 2013

Supporting Information (1)

Name/Description	Modified Date
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]	08 Oct 2009

IBIS Model

alvc00 IBIS model (REV 1.0) ibs ALVC00 4/7/2013

Ordering Information

Product	Status	Family	Function	V_CC (V)	Logic switching levels	Type	Description	Output drive capability (mA)	Package version	t_pd (ns)	f_max (MHz)	No of bits	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74ALVC00PW	Active	ALVC	NAND gates	1.65 - 3.6	TTL	NAND gates	quad 2-input NAND gate	+/- 24	SOT402-1	2.1	145	4	low	-40~85	138	6.9	64	TSSOP14	14

Package Information

Product ID	Package Description	Outline Version	Reflow/Wave Soldering	Packing	Product Status	Part NumberOrdering code(12NC)	Marking	Chemical Content	RoHS / Pb Free / RHF	LeadFree Conversion Date	EFR	IFR(FIT)	MTBF(hour)	MSL	MSL LF
74ALVC00PW		SOT402-1	SSOP-TSSOP-VSO-WAVE	Reel 13" Q1/T1	Active	74ALVC00PW,118 (9352 697 11118)	ALVC00	74ALVC00PW		week 10, 2005	123.8	3.87	2.58E8	1	1
74ALVC00PW		SOT402-1	SSOP-TSSOP-VSO-WAVE	Bulk Pack	Active	74ALVC00PW,112 (9352 697 11112)	ALVC00	74ALVC00PW		week 10, 2005	123.8	3.87	2.58E8	1	1

Quad 2-input NAND gate 74ALVC00PW

Sorting through the low voltage logic maze 74LVC_H_245A_Q100

Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100

Ground and VCC Bounce of High-Speed Integrated Circuits 74ALVC164245DGG-Q100

Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100

電圧レベルシフタ 74AVC16245DGG-Q100

Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100

ロジック製品セレクションガイド... 74LVC_H_245A_Q100

Logic selection guide 2016 74LVC_H_245A_Q100

alvc00 IBIS model 74ALVC00PW

plastic thin shrink small outline package; 14 leads; body width 4.4 mm 74LV164_Q100

SSOP-TSSOP-VSO-WAVE LPC1114FDH28

TSSOP14; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... 74LV164_Q100

74AVCM162836DGG

74LV164

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