74ALVC164245DGG-Q100: 16-bit dual supply translating transceiver; 3-state

The 74ALVC164245-Q100 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

The 74ALVC164245-Q100 is a 16-bit (dual octal) dual supply translating transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. It is designed to interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply environment.

This device can be used as two 8-bit transceivers or one 16-bit transceiver.

The direction control inputs (1DIR and 2DIR) determine the direction of the data flow. nDIR (active HIGH) enables data from nAn ports to nBn ports. nDIR (active LOW) enables data from nBn ports to nAn ports. The output enable inputs (1OE and 2OE), when HIGH, disable both nAn and nBn ports by placing them in a high-impedance OFF-state. Pins nAn, nOE and nDIR are referenced to VCC(A) and pins nBn are referenced to VCC(B).

In suspend mode, when one of the supply voltages is zero, there is no current flow from the non-zero supply towards the zero supply. The nAn outputs must be set 3-state and the voltage on the A-bus must be smaller than Vdiode (typical 0.7 V). VCC(B) ≥ VCC(A) (except in suspend mode).

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

74ALVC164245DGG-Q100: Product Block Diagram
Outline 3d SOT362-1
Data Sheets (1)
Name/DescriptionModified Date
16-bit dual supply translating transceiver; 3-state (REV 1.0) PDF (117.0 kB) 74ALVC164245_Q10014 May 2013
Application Notes (4)
Name/DescriptionModified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN1015613 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN21213 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN22313 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN25213 Mar 2013
Brochures (2)
Name/DescriptionModified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 7501751120 May 2014
Selector Guides (2)
Name/DescriptionModified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 7501728508 Jan 2015
Package Information (1)
Name/DescriptionModified Date
plastic thin shrink small outline package; 48 leads; body width 6.1 mm (REV 1.0) PDF (467.0 kB) SOT362-108 Feb 2016
Packing (1)
Name/DescriptionModified Date
TSSOP48; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 5.0) PDF (242.0 kB) SOT362-1_11815 Apr 2013
Supporting Information (1)
Name/DescriptionModified Date
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE08 Oct 2009
Ordering Information
ProductStatusFamilyVCC (V)DescriptionLogic switching levelsOutput drive capabilitytpd (ns)No of bitsfmax (MHz)Power dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pinsPackage version
74ALVC164245DGG-Q100ActiveALVC16-bit dual-supply voltage level translating transceiver (3-state)CMOS/LVTTL+/- 242.916low-40~8510423.0TSSOP4848SOT362-1
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateEFRMSLMSL LF
74ALVC164245DGG-Q100SOT362-1SSOP-TSSOP-VSO-WAVEReel 13" Q1/T1Active74ALVC164245DGG-QJ (9353 007 61118)ALVC16424574ALVC164245DGG-Q100Always Pb-free123.811