74ALVCH16823DGG: 18-bit bus-interface D-type flip-flop with reset and enable (3-State)
The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold data inputs which eliminate the need for external pull-up resistors to hold unused inputs. The74ALVCH16823 consists of two sections of nine edge-triggered flip-flops. A clock (CP) input, an output-enable (OE) input, a Master reset (MR) input and a clock-enable (CE) input are provided for each total 9-bit section.
With the clock-enable (CE) input LOW, the D-type flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition. Taking CE HIGH disables the clock buffer, thus latching the outputs. Taking the Master reset (MR) input LOW causes all the Q outputs to go LOW independently of the clock.
When OE is LOW, the contents of the flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of flip-flops.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
74ALVCH16823DGG: Product Block Diagram
Outline 3d SOT364-1
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| 18-bit bus-interface D-type flip-flop with reset and enable (3-state) (REV 2.0) PDF (103.0 kB) 74ALVCH16823 [English] | 14 Mar 2014 |
Application Notes (5)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English] | 13 Mar 2013 |
| Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English] | 13 Mar 2013 |
| Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English] | 13 Mar 2013 |
| Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English] | 15 Sep 1995 |
Brochures (2)
| Name/Description | Modified Date |
|---|---|
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Selector Guides (2)
| Name/Description | Modified Date |
|---|---|
| ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
| Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| plastic thin shrink small outline package; 56 leads; body width 6.1 mm (REV 1.0) PDF (506.0 kB) SOT364-1 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| TSSOP56; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 4.0) PDF (248.0 kB) SOT364-1_118 [English] | 15 Apr 2013 |
Supporting Information (1)
| Name/Description | Modified Date |
|---|---|
| Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English] | 08 Oct 2009 |
IBIS Model
- alvch16823 IBIS model (REV 1.0) ibs ALVCH16823 4/7/2013
Ordering Information
| Product | Status | Family | VCC (V) | Function | Logic switching levels | Description | Output drive capability (mA) | Package version | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74ALVCH16823DGG | Active | ALVC | 1.2 - 3.6 | D-type flip-flops | TTL | positive-edge trigger (3-state) | +/- 24 | SOT364-1 | 2.1 | 350 | low | -40~85 | 93 | 21.0 | TSSOP56 | 56 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74ALVCH16823DGG | | SOT364-1 | SSOP-TSSOP-VSO-WAVE | Tube in Drypack | Active | 74ALVCH16823DGGS (9352 590 30512) | ALVCH16823 | 74ALVCH16823DGG |    | Always Pb-free | 123.8 | 3.87 | 2.58E8 | 1 | 1 |
| Reel 13" Q1/T1 in Drypack | Active | 74ALVCH16823DGGY (9352 590 30518) | ALVCH16823 | 74ALVCH16823DGG | | Always Pb-free | 123.8 | 3.87 | 2.58E8 | 1 | 1 | ||||
| Bulk Pack | Discontinued | 74ALVCH16823DGG:11 (9352 590 30112) | ALVCH16823 | 74ALVCH16823DGG | | week 2, 2006 | 123.8 | 3.87 | 2.58E8 | 1 | 1 |
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
- Ground and VCC Bounce of High-Speed Integrated Circuits 74ALVC164245DGG-Q100
- Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100
- Interfacing 3 Volt and 5 Volt Applications 74LVC377PW
- 電圧レベルシフタ 74AVC16245DGG-Q100
- Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
- ロジック製品セレクションガイド... 74LVC_H_245A_Q100
- Logic selection guide 2016 74LVC_H_245A_Q100
- TSSOP56; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... pcf8576d_automotive
- alvch16823 IBIS model 74ALVCH16823DL
- plastic thin shrink small outline package; 56 leads; body width 6.1 mm pcf8576d_automotive
- SSOP-TSSOP-VSO-WAVE LPC1114FDH28
- 74ALVT16823
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