74AUP1G158GS: Low-power 2-input multiplexer; inverting
The 74AUP1G158 is a single 2-input multiplexer which select data from two data inputs (I0 and I1) under control of a common data select input (S). The state of the common data select input determines the particular register from which the data comes. The output (Y) presents the selected data in the complement (inverted) form.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
74AUP1G158GS: Product Block Diagram
sot1202_3d
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Low-power 2-input multiplexer; inverting (REV 5.0) PDF (198.0 kB) 74AUP1G158 [English] | 03 Aug 2012 |
Application Notes (2)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English] | 06 May 2011 |
Brochures (3)
| Name/Description | Modified Date |
|---|---|
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English] | 13 Oct 2014 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Selector Guides (2)
| Name/Description | Modified Date |
|---|---|
| ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
| Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm (REV 1.0) PDF (192.0 kB) SOT1202 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| Reversed product orientation 12NC ending 132 (REV 2.0) PDF (92.0 kB) SOT1202_132 [English] | 04 Apr 2013 |
Supporting Information (1)
| Name/Description | Modified Date |
|---|---|
| MAR_SOT1202 Topmark (REV 1.0) PDF (49.0 kB) MAR_SOT1202 [English] | 03 Jun 2013 |
IBIS Model
- aup1g158 IBIS model (REV 2.0) ibs AUP1G158 12/22/2014
Ordering Information
| Product | Status | Family | VCC (V) | Function | Logic switching levels | Description | Output drive capability (mA) | Package version | tpd (ns) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP1G158GS | Active | AUP | 1.1 - 3.6 | Digital multiplexers | CMOS | inverting | 1.9/-1.9 | SOT1202 | 3.2 | ultra low | -40~125 | 272 | 14.8 | 177 | XSON6 | 6 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP1G158GS | | SOT1202 | Reel 7" Q1/T1, Q3/T4 | Active | 74AUP1G158GS,132 (9352 928 52132) | aU | 74AUP1G158GS |    | Always Pb-free | 1 | 1 |
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- ロジック製品セレクションガイド... 74LVC_H_245A_Q100
- Logic selection guide 2016 74LVC_H_245A_Q100
- MAR_SOT1202 Topmark NCX2200GS
- aup1g158 IBIS model 74AUP1G158GW
- XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm NCX2200GS
- Reversed product orientation 12NC ending 132 NTS0101
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