74AUP1G32GN: Low-power 2-input OR-gate
The 74AUP1G32 provides the single 2-input OR function.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
74AUP1G32GN: Product Block Diagram
Outline 3d SOT1115
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Low-power 2-input OR-gate (REV 7.0) PDF (344.0 kB) 74AUP1G32 [English] | 08 Jul 2013 |
Application Notes (2)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English] | 06 May 2011 |
Brochures (3)
| Name/Description | Modified Date |
|---|---|
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English] | 13 Oct 2014 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Selector Guides (2)
| Name/Description | Modified Date |
|---|---|
| ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
| Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| extremely thin small outline package; no leads; 6 terminals (REV 1.0) PDF (176.0 kB) SOT1115 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| Reversed product orientation 12NC ending 132 (REV 2.0) PDF (92.0 kB) SOT1115_132 [English] | 04 Apr 2013 |
Supporting Information (1)
| Name/Description | Modified Date |
|---|---|
| MAR_SOT1115 Topmark (REV 1.0) PDF (47.0 kB) MAR_SOT1115 [English] | 03 Jun 2013 |
IBIS Model
- 74AUP1G32 IBIS model (REV 1.0) ibs AUP1G32 12/15/2014
Ordering Information
| Product | Status | Family | VCC (V) | Function | Description | Type | Logic switching levels | Package version | Output drive capability (mA) | tpd (ns) | fmax (MHz) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP1G32GN | Active | AUP | 1.1 - 3.6 | OR gates | single 2-input OR gate | OR gates | CMOS | SOT1115 | +/- 1.9 | 7.9 | 70 | 1 | ultra low | -40~125 | 334 | 22.6 | 207 | XSON6 | 6 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP1G32GN | | SOT1115 | Reel 7" Q1/T1, Q3/T4 | Active | 74AUP1G32GN,132 (9352 917 35132) | pG | 74AUP1G32GN |    | Always Pb-free | 1 | 1 |
- Low-power 2-input OR-gate 74AUP1G32GW
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- Pin FMEA for AUP family 74AUP1T34GW-Q100
- 電圧レベルシフタ 74AVC16245DGG-Q100
- NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
- Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
- ロジック製品セレクションガイド... 74LVC_H_245A_Q100
- Logic selection guide 2016 74LVC_H_245A_Q100
- MAR_SOT1115 Topmark 74AUP1G332
- 74AUP1G32 IBIS model 74AUP1G32GW
- SOT1115 74AUP1G332
- Reel 7" Q1/T1, Q3/T4 74AUP1G332
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