74AUP1G57GW: Low-power configurable multiple function gate

The 74AUP1G57 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter, and buffer. All inputs can be connected to VCC or GND.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

The 74AUP1G57 has Schmitt trigger inputs making it capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.

The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.

74AUP1G57GW: Product Block Diagram
74AUP1G57GW: Block Diagram
74AUP1G57GW: Block Diagram
74AUP1G57GW: Block Diagram
74AUP1G57GW: Block Diagram
74AUP1G57GW: Block Diagram
74AUP1G57GW: Block Diagram
74AUP1G57GW: Block Diagram
SOT363
Data Sheets (1)
Name/DescriptionModified Date
Low-power configurable multiple function gate (REV 7.0) PDF (254.0 kB) 74AUP1G57 [English]16 Sep 2015
Application Notes (3)
Name/DescriptionModified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English]06 May 2011
PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English]30 Oct 2002
Brochures (3)
Name/DescriptionModified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
Selector Guides (2)
Name/DescriptionModified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
Package Information (1)
Name/DescriptionModified Date
plastic surface-mounted package; 6 leads (REV 1.0) PDF (246.0 kB) SOT363_1 [English]08 Feb 2016
Packing (1)
Name/DescriptionModified Date
Tape reel SMD; reversed product orientation 12NC ending 125 (REV 1.0) PDF (188.0 kB) SOT363_125 [English]20 Nov 2012
Supporting Information (3)
Name/DescriptionModified Date
Reflow Soldering Profile (REV 1.0) PDF (34.0 kB) REFLOW_SOLDERING_PROFILE [English]30 Sep 2013
Wave Soldering Profile (REV 1.0) PDF (20.0 kB) WAVE_SOLDERING_PROFILE [English]30 Sep 2013
MAR_SOT363 Topmark (REV 1.0) PDF (104.0 kB) MAR_SOT363 [English]03 Jun 2013
IBIS Model
Ordering Information
ProductStatusFamilyFunctionVCC (V)TypeDescriptionLogic switching levelsOutput drive capability (mA)Package versiontpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AUP1G57GWActiveAUPConfigurable multiple function gates1.1 - 3.6Configurable gatesSchmitt triggerCMOS+/- 1.9SOT3638.7701ultra low-40~12526438.6153TSSOP66
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateEFRIFR(FIT)MTBF(hour)MSLMSL LF
74AUP1G57GWSOT363Reflow_Soldering_Profile Wave_Soldering_Profile
Reflow_Soldering_Profile Wave_Soldering_Profile
Reel 7" Q3/T4, ReverseActive74AUP1G57GW,125 (9352 799 57125)aC74AUP1G57GWAlways Pb-free0.03.293.04E811
Low-power configurable multiple function gate 74AUP1G57GX
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Pin FMEA for AUP family 74AUP1T34GW-Q100
PicoGate Logic footprints NX3L4684
電圧レベルシフタ 74AVC16245DGG-Q100
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
MAR_SOT363 Topmark BSS84AKS
aup1g57 IBIS model 74AUP1G57GW
plastic surface-mounted package; 6 leads BSS84AKS
Reflow_Soldering_Profile Wave_Soldering_Profile LPC1112FD20
Reflow_Soldering_Profile Wave_Soldering_Profile LPC1112FD20
Tape reel SMD; reversed product orientation 12NC ending 125 74LVC2G17_Q100
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