74AUP1T45GN: Low-power dual supply translating transceiver; 3-state

The 74AUP1T45 is a single bit transceiver featuring two data input-outputs (A and B), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)) which enable bidirectional level translation. Both VCC(A) and VCC(B) can be supplied at any voltage between 1.1 V and 3.6 V making the device suitable for interfacing between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A and DIR are referenced to VCC(A) and pin B is referenced to VCC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows transmission from B to A.

Schmitt trigger action on all inputs makes the circuit tolerant of slower input rise and fall times across the entire VCC(A) and VCC(B) ranges. The device ensures low static and dynamic power consumption and is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND, both A and B are in the high-impedance OFF-state.

74AUP1T45GN: Product Block Diagram

Outline 3d SOT1115

Data Sheets (1)

Name/Description	Modified Date
Low-power dual supply translating transceiver; 3-state (REV 5.0) PDF (279.0 kB) 74AUP1T45 [English]	09 Aug 2012

Application Notes (1)

Name/Description	Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]	13 Mar 2013

Brochures (2)

Name/Description	Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]	16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]	20 May 2014

Selector Guides (4)

Name/Description	Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]	19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]	08 Jan 2015
Application guide: Flat-panel TV sets (REV 2.1) PDF (3.2 MB) 75017085 [English]	13 Mar 2012
Application guide; Portable devices and mobile handsets (REV 2.0) PDF (15.4 MB) 75017090 [English]	13 Mar 2012

Package Information (1)

Name/Description	Modified Date
extremely thin small outline package; no leads; 6 terminals (REV 1.0) PDF (176.0 kB) SOT1115 [English]	08 Feb 2016

Packing (1)

Name/Description	Modified Date
Reversed product orientation 12NC ending 132 (REV 2.0) PDF (92.0 kB) SOT1115_132 [English]	04 Apr 2013

Supporting Information (1)

Name/Description	Modified Date
MAR_SOT1115 Topmark (REV 1.0) PDF (47.0 kB) MAR_SOT1115 [English]	03 Jun 2013

IBIS Model

aup1t45 IBIS model (REV 2.0) ibs AUP1T45 12/22/2014

Ordering Information

Product	Status	Family	V_CC(A) (V)	Function	Description	V_CC(B) (V)	Logic switching levels	Package version	Output drive capability (mA)	t_pd (ns)	No of bits	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74AUP1T45GN	Active	AUP	1.1 - 3.6	Level shifters/translators	single dual-supply voltage level translating transceiver (3-state)	1.1 - 3.6	CMOS	SOT1115	+/- 1.9	15.6	1	ultra low	-40~125	295	15.5	183	XSON6	6