74AUP1Z04GS: Low-power X-tal driver with enable and internal transistor

The 74AUP1Z04 combines the functions of the 74AUP1GU04 and 74AUP1G04 with enable circuitry and an internal bias resistor to provide a device optimized for use in crystal oscillator applications.

When not in use the EN input can be driven HIGH, putting the device in a low power disable mode with X1 pulled HIGH via RPU, X2 set LOW and Y set HIGH. Schmitt trigger action at the EN input makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF at output Y. The IOFF circuitry disables the output Y, preventing the damaging backflow current through the device when it is powered down.

The integration of the two devices into the 74AUP1Z04 produces the benefits of a compact footprint, lower power dissipation and stable operation over a wide range of frequency and temperature.

74AUP1Z04GS: Product Block Diagram
sot1202_3d
Data Sheets (1)
Name/DescriptionModified Date
Low-power X-tal driver with enable and internal transistor (REV 5.0) PDF (240.0 kB) 74AUP1Z04 [English]09 Aug 2012
Application Notes (1)
Name/DescriptionModified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Brochures (4)
Name/DescriptionModified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
NXP® Logic Demo Board Kit (REV 1.0) PDF (1.4 MB) 75017059 [English]02 Apr 2013
Easy test and evaluation of the 74AUP1Z04 (REV 1.0) PDF (2.3 MB) 75016907 [English]12 Feb 2013
Selector Guides (2)
Name/DescriptionModified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
Package Information (1)
Name/DescriptionModified Date
XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm (REV 1.0) PDF (192.0 kB) SOT1202 [English]08 Feb 2016
Packing (1)
Name/DescriptionModified Date
Reversed product orientation 12NC ending 132 (REV 2.0) PDF (92.0 kB) SOT1202_132 [English]04 Apr 2013
Supporting Information (1)
Name/DescriptionModified Date
MAR_SOT1202 Topmark (REV 1.0) PDF (49.0 kB) MAR_SOT1202 [English]03 Jun 2013
IBIS Model
Ordering Information
ProductStatusFamilyFunctionVCC (V)Logic switching levelsTypeDescriptionPackage versionOutput drive capability (mA)tpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AUP1Z04GSActiveAUPCombination1.1 - 3.6CMOSCombination gatescrystal driver with enable and internal resistorSOT1202+/- 1.95.6701ultra low-40~12527214.8177XSON66
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateMSLMSL LF
74AUP1Z04GSSOT1202Reel 7" Q1/T1, Q3/T4Active74AUP1Z04GS,132 (9352 928 83132)a474AUP1Z04GSAlways Pb-free11
Low-power X-tal driver with enable and internal transistor 74AUP1Z04GW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
電圧レベルシフタ 74AVC16245DGG-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
NXP® Logic Demo Board Kit NX5DV330
Easy test and evaluation of the 74AUP1Z04 74AUP1Z04GW
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
MAR_SOT1202 Topmark NCX2200GS
aup1z04 IBIS model 74AUP1Z04GW
XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm NCX2200GS
Reversed product orientation 12NC ending 132 NTS0101
74AVCM162836DGG
74LVC2G17