74AUP2G00GS: Low-power dual 2-input NAND gate
The 74AUP2G00 provides dual 2-input NAND function.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.
74AUP2G00GS: Product Block Diagram
sot1203_3d
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| low-power dual 2-input NAND gate (REV 9.0) PDF (221.0 kB) 74AUP2G00 [English] | 28 Oct 2016 |
Application Notes (2)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English] | 06 May 2011 |
Brochures (3)
| Name/Description | Modified Date |
|---|---|
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English] | 13 Oct 2014 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Selector Guides (2)
| Name/Description | Modified Date |
|---|---|
| ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
| Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| extremely thin small outline package; no leads; 8 terminals (REV 1.0) PDF (188.0 kB) SOT1203 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| Standard product orientation 12NC ending 115 (REV 1.0) PDF (88.0 kB) SOT1203_115 [English] | 03 Jul 2013 |
Supporting Information (1)
| Name/Description | Modified Date |
|---|---|
| MAR_SOT1203 Topmark (REV 1.0) PDF (73.0 kB) MAR_SOT1203 [English] | 03 Jun 2013 |
IBIS Model
- aup2g00 IBIS model (REV 1.1) ibs AUP2G00 4/8/2013
Ordering Information
| Product | Status | Family | Function | VCC (V) | Logic switching levels | Type | Description | Package version | Output drive capability (mA) | tpd (ns) | fmax (MHz) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP2G00GS | Active | AUP | NAND gates | 1.1 - 3.6 | CMOS | NAND gates | dual 2-input NAND gate | SOT1203 | +/- 1.9 | 8.3 | 70 | 2 | ultra low | -40~125 | 276 | 10.8 | 146 | XSON8 | 8 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP2G00GS | | SOT1203 | Reel 7" Q1/T1 | Active | 74AUP2G00GS,115 (9352 927 78115) | pA | 74AUP2G00GS |    | Always Pb-free | 1 | 1 |
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