74AUP2G157GS: Low-power 2-input multiplexer

The 74AUP2G157 is a single 2-input multiplexer which select data from two data inputs (I0 and I1) under control of a common data select input (S). The state of the common data select input determines the particular register from which the data comes. The output (Y, Y) presents the selected data in the true (non-inverted) and complement form. The enable input (E) is active LOW. When E is HIGH, the output Y is forced LOW and the output Y is forced HIGH regardless of all other input conditions.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

74AUP2G157GS: Product Block Diagram
sot1203_3d
Data Sheets (1)
Name/DescriptionModified Date
Low-power 2-input multiplexer (REV 7.0) PDF (294.0 kB) 74AUP2G157 [English]18 Jan 2013
Application Notes (2)
Name/DescriptionModified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English]06 May 2011
Brochures (3)
Name/DescriptionModified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
Selector Guides (2)
Name/DescriptionModified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
Package Information (1)
Name/DescriptionModified Date
extremely thin small outline package; no leads; 8 terminals (REV 1.0) PDF (188.0 kB) SOT1203 [English]08 Feb 2016
Packing (1)
Name/DescriptionModified Date
Standard product orientation 12NC ending 115 (REV 1.0) PDF (88.0 kB) SOT1203_115 [English]03 Jul 2013
Supporting Information (1)
Name/DescriptionModified Date
MAR_SOT1203 Topmark (REV 1.0) PDF (73.0 kB) MAR_SOT1203 [English]03 Jun 2013
IBIS Model
Ordering Information
ProductStatusFamilyFunctionVCC (V)Logic switching levelsDescriptionOutput drive capability (mA)Package versiontpd (ns)Power dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AUP2G157GSActiveAUPDigital multiplexers1.1 - 3.6CMOSsingle 2-input multiplexer1.9/-1.9SOT12033.4ultra low-40~12527610.8146XSON88
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateMSLMSL LF
74AUP2G157GSSOT1203Reel 7" Q1/T1Active74AUP2G157GS,115 (9352 927 83115)aP74AUP2G157GSAlways Pb-free11
Low-power 2-input multiplexer 74AUP2G157GT
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Pin FMEA for AUP family 74AUP1T34GW-Q100
電圧レベルシフタ 74AVC16245DGG-Q100
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
MAR_SOT1203 Topmark 74AXP2T3407GS
aup2g157 IBIS model 74AUP2G157GT
SOT1203 74AXP2T3407GS
Reel 7" Q1/T1 74AXP2T3407GS
74AVCM162836DGG
74LVC3G17