74AUP2G240: Low-power dual inverting buffer/line driver; 3-state
The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (nOE). A HIGH level at pin nOE causes the output to assume a high-impedance OFF-state.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
This device has the input-disable feature, which allows floating input signals. The inputs are disabled when the output enable input nOE is HIGH.
74AUP2G240: Product Block Diagram
Outline 3d SOT1116
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Low-power dual inverting buffer/line driver; 3-state (REV 8.0) PDF (293.0 kB) 74AUP2G240 [English] | 24 Jan 2013 |
Application Notes (4)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English] | 06 May 2011 |
| MicroPak soldering information (REV 2.0) PDF (245.0 kB) AN10343 [English] | 30 Dec 2010 |
| PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English] | 30 Oct 2002 |
Brochures (3)
| Name/Description | Modified Date |
|---|---|
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English] | 13 Oct 2014 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Selector Guides (2)
| Name/Description | Modified Date |
|---|---|
| ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
| Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
Package Information (7)
| Name/Description | Modified Date |
|---|---|
| Plastic extremely thin quad flat package; no leads; 8 terminals (REV 1.3) PDF (206.0 kB) SOT902-2 [English] | 14 Jul 2016 |
| plastic very thin shrink small outline package; 8 leads; body width 2.3 mm (REV 1.1) PDF (245.0 kB) SOT765-1 [English] | 05 Jul 2016 |
| extremely thin small outline package; no leads; 8 terminals (REV 1.0) PDF (200.0 kB) SOT1089 [English] | 08 Feb 2016 |
| extremely thin small outline package; no leads; 8 terminals (REV 1.0) PDF (188.0 kB) SOT1116 [English] | 08 Feb 2016 |
| extremely thin small outline package; no leads; 8 terminals (REV 1.0) PDF (188.0 kB) SOT1203 [English] | 08 Feb 2016 |
| plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm (REV 1.0) PDF (201.0 kB) SOT833-1 [English] | 08 Feb 2016 |
| plastic extremely thin small outline package; no leads; 8 terminals; body 3 x 2 x 0.5 mm (REV 1.0) PDF (190.0 kB) SOT996-2 [English] | 08 Feb 2016 |
Packing (7)
Supporting Information (4)
| Name/Description | Modified Date |
|---|---|
| MAR_SOT1089 Topmark (REV 1.0) PDF (76.0 kB) MAR_SOT1089 [English] | 03 Jun 2013 |
| MAR_SOT1116 Topmark (REV 1.0) PDF (73.0 kB) MAR_SOT1116 [English] | 03 Jun 2013 |
| MAR_SOT1203 Topmark (REV 1.0) PDF (73.0 kB) MAR_SOT1203 [English] | 03 Jun 2013 |
| MAR_SOT833 Topmark (REV 1.0) PDF (75.0 kB) MAR_SOT833 [English] | 03 Jun 2013 |
IBIS Model
- aup2g240 IBIS model (REV 1.1) ibs AUP2G240 4/8/2013
Ordering Information
| Product | Status |
|---|---|
| 74AUP2G240GF | Active |
| 74AUP2G240DC | Active |
| 74AUP2G240GS | Active |
| 74AUP2G240GT | Active |
| 74AUP2G240GD | Active |
| 74AUP2G240GM | Active |
| 74AUP2G240GN | Active |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP2G240GS |  | SOT1203 | Reel 7" Q1/T1 | Active | 74AUP2G240GS,115 (9352 927 84115) | p2 | 74AUP2G240GS |    | Always Pb-free | 1 | 1 | ||||
| 74AUP2G240GM |  | SOT902-2 | Reel 7" Q3/T4, Reverse | Active | 74AUP2G240GM,125 (9352 814 37125) | p40 | 74AUP2G240GM | | Always Pb-free | 0.0 | 3.29 | 3.04E8 | 1 | 1 | |
| 74AUP2G240GF |  | SOT1089 | Reel 7" Q1/T1 | Active | 74AUP2G240GF,115 (9352 914 79115) | p2 | 74AUP2G240GF | | Always Pb-free | 1 | 1 | ||||
| 74AUP2G240DC |  | SOT765-1 | Reel 7" Q3/T4, Reverse | Active | 74AUP2G240DC,125 (9352 807 36125) | p40 | 74AUP2G240DC |  | Always Pb-free | 0.0 | 3.29 | 3.04E8 | 1 | 1 | |
| 74AUP2G240GT |  | SOT833-1 | Reel 7" Q1/T1 | Active | 74AUP2G240GT,115 (9352 807 37115) | p40 | 74AUP2G240GT | | Always Pb-free | 0.0 | 3.29 | 3.04E8 | 1 | 1 | |
| 74AUP2G240GN | | SOT1116 | Reel 7" Q1/T1 | Active | 74AUP2G240GN,115 (9352 922 24115) | p2 | 74AUP2G240GN | | Always Pb-free | 1 | 1 | ||||
| 74AUP2G240GD |  | SOT996-2 | Reel 7" Q3/T4, Reverse | Active | 74AUP2G240GD,125 (9352 888 75125) | p40 | 74AUP2G240GD | | Always Pb-free | 0.0 | 3.29 | 3.04E8 | 1 | 1 |
- Low-power dual inverting buffer/line driver; 3-state 74AUP2G240GT
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
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- NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
- Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
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- Logic selection guide 2016 74LVC_H_245A_Q100
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- XSON8(U); Reel pack, Reverse; SMD, 7" Q3/T4 Standard product orientation Orderable part number ending ,125 or... 74AHC_T_3G14_Q100
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