74AUP2G57GU: Low-power dual PCB configurable multiple function gate
The 74AUP2G57 is a dual configurable multiple function gate with Schmitt-trigger inputs. Each gate within the device can be configured as any of the following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND.
This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
74AUP2G57GU: Product Block Diagram
sot1160-1_3d
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Low-power dual PCB configurable multiple function gate (REV 2.0) PDF (221.0 kB) 74AUP2G57 [English] | 02 Dec 2015 |
Brochures (2)
| Name/Description | Modified Date |
|---|---|
| NXP® Dual PCB Configurable Logic (REV 1.0) PDF (3.0 MB) 75017615 [English] | 07 Nov 2014 |
| NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English] | 13 Oct 2014 |
Selector Guides (2)
| Name/Description | Modified Date |
|---|---|
| ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
| Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| plastic, extremely thin quad flat package; no leads; 10 terminals (REV 1.0) PDF (207.0 kB) SOT1160-1 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| Standard product orientation 12NC ending 115 (REV 2.0) PDF (97.0 kB) SOT1160-1_115 [English] | 04 Apr 2013 |
IBIS Model
- 74AUP2G57 IBIS model (REV 1.0) ibs AUP2G57 4/3/2015
Ordering Information
| Product | Status | Family | Function | VCC (V) | Logic switching levels | Type | Description | Output drive capability (mA) | Package version | tpd (ns) | fmax (MHz) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP2G57GU | Active | AUP | dual configurable gate; Schmitt trigger | 1.1 - 3.6 | CMOS | Configurable gates | Configurable | +/- 1.9 | SOT1160-1 | 8.7 | 70 | 2 | ultra low | -40~125 | 142 | 48.0 | XQFN10 | 10 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP2G57GU | | SOT1160-1 | Reel 7" Q1/T1 | Active | 74AUP2G57GUX (9353 044 74115) | aC | 74AUP2G57GU |    | Always Pb-free | 1 | 1 |
- NXP® Dual PCB Configurable Logic 74AUP2G98GU
- NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
- ロジック製品セレクションガイド... 74LVC_H_245A_Q100
- Logic selection guide 2016 74LVC_H_245A_Q100
- 74AUP2G57 IBIS model 74AUP2G57GU
- plastic, extremely thin quad flat package; no leads; 10 terminals NX5L2750CGU
- Standard product orientation 12NC ending 115 NX5L2750CGU
- 74AVCM162836DGG
- NTS0103GU10
