74AUP2G97: Low-power dual PCB configurable multiple function gate

The 74AUP2G97 is a dual configurable multiple function gate with Schmitt-trigger inputs. Each gate within the device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND.

This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

sot1160-1_3d

Data Sheets (1)

Name/Description	Modified Date
Low-power dual PCB configurable multiple function gate (REV 2.0) PDF (221.0 kB) 74AUP2G97 [English]	02 Dec 2015

Brochures (2)

Name/Description	Modified Date
NXP® Dual PCB Configurable Logic (REV 1.0) PDF (3.0 MB) 75017615 [English]	07 Nov 2014
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]	13 Oct 2014

Selector Guides (2)

Name/Description	Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]	19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]	08 Jan 2015

Package Information (3)

Name/Description	Modified Date
plastic thin shri small outline package; 10 leads; body width 3 mm (REV 1.1) PDF (256.0 kB) SOT552-1 [English]	07 Jun 2016
plastic extremely thin small outline package; no leads; 10 terminals (REV 1.0) PDF (160.0 kB) SOT1081-2 [English]	08 Feb 2016
plastic, extremely thin quad flat package; no leads; 10 terminals (REV 1.0) PDF (207.0 kB) SOT1160-1 [English]	08 Feb 2016

Packing (2)

Name/Description	Modified Date
TSSOP10; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 1.0) PDF (269.0 kB) SOT552-1_118 [English]	16 Apr 2013
Standard product orientation 12NC ending 115 (REV 2.0) PDF (97.0 kB) SOT1160-1_115 [English]	04 Apr 2013

Supporting Information (3)

Name/Description	Modified Date
Reflow Soldering Profile (REV 1.0) PDF (34.0 kB) REFLOW_SOLDERING_PROFILE [English]	30 Sep 2013
Wave Soldering Profile (REV 1.0) PDF (20.0 kB) WAVE_SOLDERING_PROFILE [English]	30 Sep 2013
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]	08 Oct 2009

IBIS Model

74AUP2G98 IBIS model (REV 1.0) ibs AUP2G97 4/3/2015

Ordering Information

Product	Status	Family	Type	Description	V_CC (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	f_max (MHz)	No of bits	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	No of pins	Package name	Package version
74AUP2G97DP	Active	AUP	Configurable gates	Schmitt trigger	1.1 - 3.6	CMOS	+/- 1.9	8.7	70	2	ultra low	-40~125	120	30.0	10	TSSOP10	SOT552-1
74AUP2G97GU	Active	AUP	Configurable gates	Configurable	1.1 - 3.6	CMOS	+/- 1.9	8.7	70	2	ultra low	-40~125	142	48.0	10	XQFN10	SOT1160-1
74AUP2G97GF	Active	AUP	Configurable gates	Configurable	1.1 - 3.6	CMOS	+/- 1.9	8.7	70	2	ultra low	-40~125	192	97.0	10	XSON10	SOT1081-2

Package Information

Product ID	Outline Version	Reflow/Wave Soldering	Packing	Product Status	Part NumberOrdering code(12NC)	Marking	Chemical Content	LeadFree Conversion Date	MSL	MSL LF
74AUP2G97GF	SOT1081-2		Reel 7" Q1/T1	Active	74AUP2G97GFX (9353 044 82115)	aV	74AUP2G97GF	Always Pb-free	1	1
74AUP2G97DP	SOT552-1	Reflow_Soldering_Profile SSOP-TSSOP-VSO-WAVE Reflow_Soldering_Profile SSOP-TSSOP-VSO-WAVE	Reel 13" Q1/T1	Active	74AUP2G97DPJ (9353 044 81118)	Standard Marking	74AUP2G97DP	Always Pb-free	1	1
74AUP2G97GU	SOT1160-1		Reel 7" Q1/T1	Active	74AUP2G97GUX (9353 044 84115)	aV	74AUP2G97GU	Always Pb-free	1	1