74AVCH4T245GU: 4-bit dual supply translating transceiver with configurable voltage translation; 3-state

The 74AVCH4T245 is a 4-bit, dual supply transceiver that enables bidirectional level translation. The device can be used as two 2-bit transceivers or as a 4-bit transceiver. It features two 2-bit input-output ports (nAn and nBn), a direction control input (nDIR), a output enable input (nOE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nAn, nOE and nDIR are referenced to VCC(A) and pins nBn are referenced to VCC(B). A HIGH on nDIR allows transmission from nAn to nBn and a LOW on nDIR allows transmission from nBn to nAn. The output enable input (nOE) can be used to disable the outputs so the buses are effectively isolated.

The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both nAn and nBn outputs are in the high-impedance OFF-state. The bus hold circuitry on the powered-up side always stays active.

The 74AVCH4T245 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

sot1161-1_3d
Data Sheets (1)
Name/DescriptionModified Date
4-bit dual supply translating transceiver with configurable voltage translation; 3-state (REV 5.0) PDF (192.0 kB) 74AVCH4T245 [English]17 Dec 2015
Application Notes (1)
Name/DescriptionModified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Brochures (2)
Name/DescriptionModified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
Package Information (1)
Name/DescriptionModified Date
plastic, extermely thin quad flat package; no leads; 16 terminals (REV 1.0) PDF (217.0 kB) SOT1161-1 [English]08 Feb 2016
Packing (1)
Name/DescriptionModified Date
Standard product orientation 12NC ending 115 (REV 2.0) PDF (88.0 kB) SOT1161-1_115 [English]05 Apr 2013
Ordering Information
ProductStatusFamilyFunctionVCC(A) (V)DescriptionVCC(B) (V)Logic switching levelsPackage versionOutput drive capability (mA)tpd (ns)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AVCH4T245GUActiveAVC(M)Level shifters/translators0.8 - 3.64-bit dual-supply voltage translating transceiver with bus hold (3-state)0.8 - 3.6CMOS/LVTTLSOT1161-1+/- 122.14very low-40~125994.188XQFN1616
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateMSLMSL LF
74AVCH4T245GUSOT1161-1Reel 7" Q1/T1Active74AVCH4T245GU,115 (9352 933 86115)Standard Marking74AVCH4T245GUAlways Pb-free11
4-bit dual supply translating transceiver with configurable voltage translation; 3-state 74AVCH4T245PW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
電圧レベルシフタ 74AVC16245DGG-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
plastic, extermely thin quad flat package; no leads; 16 terminals pcal6408a
Standard product orientation 12NC ending 115 pcal6408a
NTBA104