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74HC(T)193-Q100: Presettable synchronous 4-bit binary up/down counter

The 74HC193-Q100; 74HCT193-Q100 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held HIGH, the device counts up. If the CPD clock is pulsed while CPU is held HIGH, the device counts down. Only one clock input can be held HIGH at any time to guarantee predictable behavior. The device can be cleared at any time by the asynchronous master reset input (MR). It may also be loaded in parallel by activating the asynchronous parallel load input (PL). The terminal count up (TCU) and terminal count down (TCD) outputs are normally HIGH. When the circuit has reached the maximum count state of 15, the next HIGH-to-LOW transition of CPU causes TCU to go LOW. TCU remains LOW until CPU goes HIGH again, duplicating the count up clock. Likewise, the TCD output goes LOW when the circuit is in the zero state and the CPD goes LOW. The terminal count outputs duplicate the clock waveforms and can be used as the clock input signals to the next higher-order circuit in a multistage counter. Multistage counters are not fully synchronous, since there is a slight delay time difference added for each stage that is added. The counter may be preset by the asynchronous parallel load capability of the circuit. Information on the parallel data inputs (D0 to D3), is loaded into the counter. This information appears on the outputs (Q0 to Q3) regardless of the conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on the master reset (MR) input disables the parallel load gates. It overrides both clock inputs and sets all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that clock is interpreted as a legitimate signal and it is counted. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

74HC_T_193_Q100: Product Block Diagram

Outline 3d SOT338-1

Data Sheets (1)

Application Notes (1)

Selector Guides (2)

Package Information (3)

Packing (2)

Supporting Information (4)

Ordering Information

Package Information

Product ID	Package Description	Outline Version	Reflow/Wave Soldering	Packing	Product Status	Part NumberOrdering code(12NC)	Marking	Chemical Content	RoHS / Pb Free / RHF	LeadFree Conversion Date	EFR	MSL	MSL LF
74HC193PW-Q100		SOT403-1	SSOP-TSSOP-VSO-WAVE	Reel 13" Q1/T1	Active	74HC193PW-Q100J (9353 004 46118)	HC193	74HC193PW-Q100		Always Pb-free	84.9	1	1
74HCT193D-Q100		SOT109-1	SO-SOJ-REFLOW SO-SOJ-WAVE SO-SOJ-REFLOW SO-SOJ-WAVE	Reel 13" Q1/T1	Active	74HCT193D-Q100J (9353 004 51118)	74HCT193D	74HCT193D-Q100		Always Pb-free	84.9	1	1
74HCT193PW-Q100		SOT403-1	SSOP-TSSOP-VSO-WAVE	Reel 13" Q1/T1	Active	74HCT193PW-Q100J (9353 004 52118)	HCT193	74HCT193PW-Q100		Always Pb-free	84.9	1	1
74HC193D-Q100		SOT109-1	SO-SOJ-REFLOW SO-SOJ-WAVE SO-SOJ-REFLOW SO-SOJ-WAVE	Reel 13" Q1/T1	Active	74HC193D-Q100J (9353 004 45118)	74HC193D	74HC193D-Q100		Always Pb-free	84.9	1	1
74HC193DB-Q100		SOT338-1	SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE	Reel 13" Q1/T1	Active	74HC193DB-Q100J (9353 004 44118)	HC193	74HC193DB-Q100		Always Pb-free	84.9	1	1
74HCT193DB-Q100		SOT338-1	SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE	Reel 13" Q1/T1	Active	74HCT193DB-Q100J (9353 004 49118)	HCT193	74HCT193DB-Q100		Always Pb-free	84.9	1	1