74LV03D: Quad 2-input NAND gate
The 74LV03 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT03.
The 74LV03 provides the 2-input NAND function.
The 74LV03 has open-drain N-transistor outputs, which are not clamped by a diode connected to VCC. In the OFF-state, i.e., when one input is LOW, the output may be pulled to any voltage between GND and VOmax. This allows the device to be used as a LOW-to-HIGH or HIGH-to-LOW level shifter. For digital operation and OR-tied output applications, these devices must have a pull-up resistor to establish a logic HIGH level.
74LV03D: Product Block Diagram
sot108-1_3d
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Quad 2-input NAND gate (REV 3.0) PDF (59.0 kB) 74LV03 [English] | 03 Mar 2003 |
Application Notes (1)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
Brochures (2)
| Name/Description | Modified Date |
|---|---|
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| plastic small outline package; 14 leads; body width 3.9 mm (REV 1.0) PDF (166.0 kB) SOT108-1 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| SO14; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or J Ordering... (REV 4.0) PDF (207.0 kB) SOT108-1_118 [English] | 08 Apr 2013 |
Supporting Information (2)
| Name/Description | Modified Date |
|---|---|
| Footprint for reflow soldering (REV 1.0) PDF (9.0 kB) SO-SOJ-REFLOW [English] | 08 Oct 2009 |
| Footprint for wave soldering (REV 1.0) PDF (8.0 kB) SO-SOJ-WAVE [English] | 08 Oct 2009 |
Ordering Information
| Product | Status | Family | Function | VCC (V) | Logic switching levels | Type | Description | Output drive capability (mA) | Package version | tpd (ns) | fmax (MHz) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LV03D | Active | LV | NAND gates | 1.0 - 5.5 | TTL | NAND gates | quad 2-input NAND gate | +/- 12 | SOT108-1 | 8 | 30 | 4 | low | -40~125 | 96 | 12.2 | 54 | SO14 | 14 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LV03D | | SOT108-1 | SO-SOJ-REFLOW
SO-SOJ-WAVE SO-SOJ-REFLOW SO-SOJ-WAVE | Reel 13" Q1/T1 | Active | 74LV03D,118 (9351 758 20118) | 74LV03D | 74LV03D |    | week 30, 2004 | 144.9 | 10.23 | 9.78E7 | 1 | 1 |
| Bulk Pack | Active | 74LV03D,112 (9351 758 20112) | 74LV03D | 74LV03D | | week 30, 2004 | 144.9 | 10.23 | 9.78E7 | 1 | 1 |
- Quad 2-input NAND gate 74LV03D
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- 電圧レベルシフタ 74AVC16245DGG-Q100
- Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
- plastic small outline package; 14 leads; body width 3.9 mm 74LV164_Q100
- Footprint for reflow soldering NPIC6C596A_Q100
- Footprint for wave soldering NPIC6C596A_Q100
- SO14; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or J Ordering... 74LV164_Q100
- 74LV03D
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