74LV132PW: Quad 2-input NAND Schmitt trigger
The 74LV132 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC132 and 74HCT132.
The 74LV132 contains four 2-input NAND gates which accept standard input signals. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
The gate switches at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.
74LV132PW: Product Block Diagram
Outline 3d SOT402-1
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Quad 2-input NAND Schmitt trigger (REV 6.0) PDF (199.0 kB) 74LV132 [English] | 09 Dec 2015 |
Application Notes (1)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
Brochures (2)
| Name/Description | Modified Date |
|---|---|
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| plastic thin shrink small outline package; 14 leads; body width 4.4 mm (REV 1.0) PDF (285.0 kB) SOT402-1 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| TSSOP14; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 1.0) PDF (217.0 kB) SOT402-1_118 [English] | 08 Apr 2013 |
Supporting Information (1)
| Name/Description | Modified Date |
|---|---|
| Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English] | 08 Oct 2009 |
SPICE model
- lv Spice model (REV 1.0) ZIP LV 5/7/2013
Ordering Information
| Product | Status | Family | Function | VCC (V) | Description | Logic switching levels | Type | Output drive capability (mA) | Package version | tpd (ns) | fmax (MHz) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LV132PW | Active | LV | Schmitt-triggers | 1.0 - 5.5 | quad 2-input NAND gate Schmitt-trigger | TTL | NAND gates | +/- 12 | SOT402-1 | 10 | 30 | 4 | low | -40~125 | 130 | 4.3 | 55.6 | TSSOP14 | 14 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LV132PW | | SOT402-1 | SSOP-TSSOP-VSO-WAVE | Reel 13" Q1/T1 | Active | 74LV132PW,118 (9352 301 00118) | LV132 | 74LV132PW |    | week 10, 2005 | 144.9 | 10.23 | 9.78E7 | 1 | 1 |
| Bulk Pack | Active | 74LV132PW,112 (9352 301 00112) | LV132 | 74LV132PW | | week 10, 2005 | 144.9 | 10.23 | 9.78E7 | 1 | 1 |
- Quad 2-input NAND Schmitt trigger 74LV132PW
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- 電圧レベルシフタ 74AVC16245DGG-Q100
- Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
- lv Spice model 74LV74PW
- plastic thin shrink small outline package; 14 leads; body width 4.4 mm 74LV164_Q100
- SSOP-TSSOP-VSO-WAVE LPC1114FDH28
- TSSOP14; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... 74LV164_Q100
- 74LV132
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