74LV165AD: 8-bit parallel-in/serial-out shift register

The 74LV165A is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel-load input (PL) is LOW, parallel data from the inputs D0 to D7 are loaded into the register asynchronously. When input PL is HIGH, data enters the register serially at the input DS. It shifts one place to the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the output Q7 to the input DS of the succeeding stage.

The clock input is a gate-OR structure which allows one input to be used as an active LOW clock enable input (CE) input. The pin assignment for the inputs CP and CE is arbitrary and can be reversed for layout convenience. The LOW‑to‑HIGH transition of the input CE should only take place while CP HIGH for predictable operation.

Schmitt-trigger action at all inputs, makes the circuit tolerant for slower input rise and fall times. It is fully specified for partial-power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging current backflow through the device when it is powered down.

74LV165AD: Product Block Diagram
sot109-1_3d
Data Sheets (1)
Name/DescriptionModified Date
8-bit parallel-in/serial-out shift register (REV 4.0) PDF (190.0 kB) 74LV165A [English]28 Mar 2014
Application Notes (1)
Name/DescriptionModified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Brochures (2)
Name/DescriptionModified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
Package Information (1)
Name/DescriptionModified Date
plastic small outline package; 16 leads; body width 3.9 mm (REV 1.0) PDF (192.0 kB) SOT109-1 [English]08 Feb 2016
Packing (1)
Name/DescriptionModified Date
SO16; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or J Ordering... (REV 4.0) PDF (210.0 kB) SOT109-1_118 [English]24 Apr 2013
Supporting Information (2)
Name/DescriptionModified Date
Footprint for reflow soldering (REV 1.0) PDF (9.0 kB) SO-SOJ-REFLOW [English]08 Oct 2009
Footprint for wave soldering (REV 1.0) PDF (8.0 kB) SO-SOJ-WAVE [English]08 Oct 2009
Ordering Information
ProductStatusFamilyFunctionVCC (V)DescriptionLogic switching levelsOutput drive capability (mA)Package versiontpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74LV165ADActiveLVShift registers1.0 - 5.58-bit parallel or serial-in/serial-out shift registerTTL+/- 12SOT109-17.51158low-40~125929.351SO1616
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateEFRIFR(FIT)MTBF(hour)MSLMSL LF
74LV165ADSOT109-1SO-SOJ-REFLOW SO-SOJ-WAVE
SO-SOJ-REFLOW SO-SOJ-WAVE
Reel 13" Q1/T1Active74LV165AD,118 (9352 731 76118)74LV165AD74LV165ADweek 35, 2004144.910.239.78E711
Bulk PackActive74LV165AD,112 (9352 731 76112)74LV165AD74LV165ADweek 35, 2004144.910.239.78E711
8-bit parallel-in/serial-out shift register 74LV165APW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
電圧レベルシフタ 74AVC16245DGG-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
plastic small outline package; 16 leads; body width 3.9 mm NPIC6C596A_Q100
Footprint for reflow soldering NPIC6C596A_Q100
Footprint for wave soldering NPIC6C596A_Q100
SO16; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or J Ordering... NPIC6C596A_Q100
74LV165A
SA614A