74LVC32245AEC: 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state

The 74LVC32245A is a 32-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The device features four output enable (nOE) inputs for easy cascading and four send/receive (nDIR) inputs for direction control. Pin nOE controls the outputs so that the buses are effectively isolated.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications.

To ensure the high-impedance state during power-up or power-down, pin nOE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

74LVC32245AEC: Product Block Diagram

sot536-1_3d

Data Sheets (1)

Name/Description	Modified Date
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state (REV 3.0) PDF (150.0 kB) 74LVC32245A [English]	16 Dec 2011

Application Notes (6)

Name/Description	Modified Date
(LF)BGA Application note, ATO Innovation (REV 1.0) PDF (69.0 kB) AN1026_1 [English]	13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]	13 Mar 2013
ANLFBGA 32-Bit Logic Families in Low-profile Fine-pitch Ball Grid Array (LFBGA) Packages (REV 1.0) PDF (453.0 kB) ANLFBGA [English]	13 Mar 2013
Pin FMEA for LVC family (REV 1.0) PDF (44.0 kB) AN11009 [English]	04 Feb 2011
Power considerations when using CMOS and BiCMOS logic devices (REV 1.0) PDF (100.0 kB) AN263 [English]	05 Feb 2002
Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English]	15 Sep 1995

Selector Guides (2)

Name/Description	Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]	19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]	08 Jan 2015

Package Information (1)

Name/Description	Modified Date
plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm (REV 1.0) PDF (438.0 kB) SOT536-1 [English]	08 Feb 2016

Ordering Information

Product	Status	Family	Function	V_CC (V)	Logic switching levels	Description	Output drive capability	Package version	t_pd (ns)	No of bits	f_max (MHz)	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74LVC32245AEC	Active	LVC	Transceivers	1.2 - 3.6	CMOS/LVTTL	32-bit transceiver (3-state)	+/- 24	SOT536-1	2.2	32	175	low		60	16.0		LFBGA96	96

Package Information

Product ID	Outline Version	Packing	Product Status	Part NumberOrdering code(12NC)	Marking	Chemical Content	EFR	IFR(FIT)	MTBF(hour)	MSL	MSL LF
74LVC32245AEC	SOT536-1	Reel 13" Q1/T1 in Drypack	Active	74LVC32245AEC,518 (9352 849 53518)	VC32245A	74LVC32245AEC	123.8	3.87	2.58E8	3	4
		Tray, Bakeable, Multiple in Drypack	Active	74LVC32245AEC,557 (9352 849 53557)	VC32245A	74LVC32245AEC	123.8	3.87	2.58E8	3	4
		Tray, Bakeable, Single in Drypack	Active	74LVC32245AEC,551 (9352 849 53551)	VC32245A	74LVC32245AEC	123.8	3.87	2.58E8	3	4