74LVC374ABQ: Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state

The 74LVC374A is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an outputs enable input (OE) are common to all flip-flops.

The eight flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition.

When pin OE is LOW, the contents of the eight flip-flops is available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices as translators in mixed 3.3 V and 5 V applications.

The 74LVC374A is functionally identical to the 74LVC574A, but has a different pin arrangement.

74LVC374ABQ: Product Block Diagram
Outline 3d SOT764-1
Data Sheets (1)
Name/DescriptionModified Date
Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state (REV 3.0) PDF (219.0 kB) 74LVC374A [English]06 Dec 2012
Application Notes (5)
Name/DescriptionModified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
Pin FMEA for LVC family (REV 1.0) PDF (44.0 kB) AN11009 [English]04 Feb 2011
Power considerations when using CMOS and BiCMOS logic devices (REV 1.0) PDF (100.0 kB) AN263 [English]05 Feb 2002
Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English]15 Sep 1995
Selector Guides (2)
Name/DescriptionModified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
Package Information (1)
Name/DescriptionModified Date
plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x... (REV 1.0) PDF (190.0 kB) SOT764-1 [English]08 Feb 2016
Packing (1)
Name/DescriptionModified Date
DHVQFN20; Reel pack; SMD, 7" Q1/T1 Standard product orientation Orderable part number ending ,115 or... (REV 4.0) PDF (203.0 kB) SOT764-1_115 [English]23 Apr 2013
IBIS Model
SPICE model
Ordering Information
ProductStatusFamilyFunctionVCC (V)Logic switching levelsDescriptionPackage versionOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74LVC374ABQActiveLVCD-type flip-flops1.2 - 3.6CMOS/LVTTLpositive-edge trigger (3-state)SOT764-1+/- 242.7100low-40~125789.049DHVQFN2020
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateEFRIFR(FIT)MTBF(hour)MSLMSL LF
74LVC374ABQSOT764-1Reel 7" Q1/T1Active74LVC374ABQ,115 (9352 734 79115)LVC374A74LVC374ABQAlways Pb-free123.83.872.58E811
Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state 74LVC374APW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
Pin FMEA for LVC family 74LVC1G123_Q100
Power considerations when using CMOS and BiCMOS logic devices 74AHCT244PW
Interfacing 3 Volt and 5 Volt Applications 74LVC377PW
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
lvc374a IBIS model 74LVC374APW
lvc Spice model 74LVC3G17GT
plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x... 74LVC_H_245A_Q100
DHVQFN20; Reel pack; SMD, 7" Q1/T1 Standard product orientation Orderable part number ending ,115 or... 74LVC_H_245A_Q100
74LVC374A
74VHC_T_245