74LVC573ABX: Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

The 74LVC573A consists of eight D-type transparent latches, featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A Latch Enable (LE) input and an Output Enable (OE) input are common to all internal latches.

When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches are transparent, that is, a latch output will change each time its corresponding D-input changes. When LE is LOW, the latches store the information that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of LE.

When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices as translators in mixed 3.3 V or 5 V applications.

The 74LVC573A is functionally identical to the 74LVC373A, but has a different pin arrangement.

74LVC573ABX: Product Block Diagram
Data Sheets (1)
Name/DescriptionModified Date
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state (REV 5.0) PDF (156.0 kB) 74LVC573A [English]19 Feb 2013
Application Notes (3)
Name/DescriptionModified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
A metastability primer (REV 1.0) PDF (40.0 kB) AN219 [English]13 Mar 2013
Selector Guides (2)
Name/DescriptionModified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
Package Information (1)
Name/DescriptionModified Date
Plastic dual in-line compatible thermal enhanced extremely thin quad flat package; no leads; 20 terminals (REV 1.0) PDF (150.0 kB) SOT1045-2 [English]10 Feb 2016
IBIS Model
SPICE model
Ordering Information
ProductStatusFamilyFunctionVCC (V)DescriptionLogic switching levelsPackage versionOutput drive capability (mA)tpd (ns)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74LVC573ABXActiveLVCLatches/registered drivers1.2 - 3.6octal D-type transparent latch (3-state)TTLSOT1045-2+/- 243.48low-40~125DHXQFN2020
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateEFRIFR(FIT)MTBF(hour)MSLMSL LF
74LVC573ABXSOT1045-2Reel 7" Q1/T1Active74LVC573ABXX (9353 006 01115)LVC573A74LVC573ABXAlways Pb-free123.83.872.58E811