74LVCH16374ABX: 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

The 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered flip-flops featuring separate D-type inputs with bus hold (74LVCH16374A only) for each flip-flop and 3-state outputs for bus oriented applications. It consists of two sections of eight positive edge-triggered flip-flops. A clock input (nCP) and an output enable (nOE) are provided for each octal.

The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition.

When pin nOE is LOW, the contents of the flip-flops are available at the outputs. When pin nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input nOE does not affect the state of the flip-flops.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications.

Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs.

74LVCH16374ABX: Product Block Diagram
sot1134-2_3d
Data Sheets (1)
Name/DescriptionModified Date
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state (REV 11.0) PDF (138.0 kB) 74LVC_LVCH16374A [English]16 Jan 2013
Application Notes (2)
Name/DescriptionModified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
Brochures (1)
Name/DescriptionModified Date
Low voltage CMOS family - LVC (REV 1.0) PDF (2.6 MB) 75017668 [English]10 Jul 2015
Selector Guides (2)
Name/DescriptionModified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
Package Information (1)
Name/DescriptionModified Date
plastic compatible thermal enhanced extremely thin quad flat package; no leads (REV 1.1) PDF (217.0 kB) SOT1134-2 [English]10 Jun 2016
IBIS Model
Ordering Information
ProductStatusFamilyVCC (V)FunctionLogic switching levelsDescriptionOutput drive capability (mA)Package versiontpd (ns)fmax (MHz)Power dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74LVCH16374ABXActiveLVC1.2 - 3.6D-type flip-flopsCMOS/LVTTLpositive-edge trigger (3-state)+/- 24SOT1134-23.8150low-40~125HXQFN60U60
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateEFRIFR(FIT)MTBF(hour)MSLMSL LF
74LVCH16374ABXSOT1134-2Reel 13" Q1/T1 in DrypackActive74LVCH16374ABX,518 (9352 958 75518)LVCH16374A74LVCH16374ABXAlways Pb-free123.83.872.58E822