74HC4520PW-Q100: Dual 4-bit synchronous binary counter
The 74HC4520-Q100; 74HCT4520-Q100 are dual 4-bit internally synchronous binary
counters with two clock inputs (nCP0 and nCP1). They have buffered outputs from all 4 bit
positions (nQ0 to nQ3), and an asynchronous master reset input (nMR). The counter
advances on either the LOW-to-HIGH transition of nCP0 when nCP1 is HIGH. It also
advances on the HIGH-to-LOW transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP1
may be used as the clock input to the counter. The other clock input may be used as a
clock enable input. A HIGH on nMR resets the counter (nQ0 to nQ3 = LOW) independent
of nCP0 and nCP1. Inputs include clamp diodes. It enables the use of current limiting
resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
Outline 3d SOT403-1
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