HEF4015B: Dual 4-bit static shift register (Based on PIP HEF4015B)
The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (Q0 to Q3) and an overriding asynchronous master reset input (MR). Information present on D is shifted to the first register position, and all the data in the register is shifted one position to the right on the LOW-to-HIGH transition of CP. A HIGH on MR clears the register and forces Q0 to Q3 to LOW, independent of CP and D. The clock input’s Schmitt trigger action makes the input highly tolerant of slower clock rise and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
HEF4015B: Product Block Diagram
sot109-1_3d
Data Sheets (1)
Application Notes (1)
Brochures (2)
Package Information (1)
Supporting Information (2)
Ordering Information
| Product | Status |
|---|
| HEF4015BT | Active |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|
| HEF4015BT | | SOT109-1 | SO-SOJ-REFLOW
SO-SOJ-WAVE
SO-SOJ-REFLOW
SO-SOJ-WAVE | Reel 13" Q1/T1 CECC | Active | HEF4015BT,653
(9333 726 80653) | HEF4015BT | HEF4015BT |    | week 6, 2004 | 75.3 | 2.99 | 3.34E8 | 1 | 1 |
| Bulk Pack, CECC | Active | HEF4015BT,652
(9333 726 80652) | HEF4015BT | HEF4015BT | | week 6, 2004 | 75.3 | 2.99 | 3.34E8 | 1 | 1 |
