HEF4021BT: 8-bit static shift register
The HEF4021B is an 8-bit static shift register (parallel-to-serial converter) with a
synchronous serial data input (DS), a clock input (CP), an asynchronous active HIGH
parallel load input (PL), eight asynchronous parallel data inputs (D0 to D7) and buffered
parallel outputs from the last three stages (Q5 to Q7).
Each register stage is a D-type master-slave flip-flop with a set direct (SD) and clear direct
(CD) input. Information on D0 to D7 is asynchronously loaded into the register while PL is
HIGH, independent of CP and DS. When PL is LOW, data on DS is shifted into the first
register position and all the data in the register is shifted one position to the right on the
LOW-to-HIGH transition of CP. Schmitt trigger action makes the clock input highly tolerant
of slower rise and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.
HEF4021BT: Product Block Diagram
sot109-1_3d
Data Sheets (1)
Application Notes (1)
Brochures (2)
Package Information (1)
Packing (1)
Supporting Information (2)
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|
| HEF4021BT | | SOT109-1 | SO-SOJ-REFLOW
SO-SOJ-WAVE
SO-SOJ-REFLOW
SO-SOJ-WAVE | Reel 13" Q1/T1 CECC | Active | HEF4021BT,653
(9333 727 40653) | HEF4021BT | HEF4021BT |    | week 12, 2005 | 75.3 | 2.99 | 3.34E8 | 1 | 1 |
| Bulk Pack, CECC | Active | HEF4021BT,652
(9333 727 40652) | HEF4021BT | HEF4021BT | | week 12, 2005 | 75.3 | 2.99 | 3.34E8 | 1 | 1 |
