MC100EP33: 3.3 V / 5.0 V ECL ÷·4 Divider

The MC10/100EP33 is an integrated divide by 4 divider. The differential clock inputs.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage.VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5mA. When not used, VBB should be left open.The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple EP33's in a system.The 100 Series contains temperature compensation.

Features
  • 320ps Propagation Delay
  • Maximum Frequency > 4 GHz Typical
  • PECL Mode Operating Range: VCC= 3.0 V to 5.5 V with VEE= 0 V
  • NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • Q Output will default LOW with inputs open or at VEE
  • VBB Output
  • Pb-Free Packages are Available
Applications
  • Phase Lock Loops
Application Notes (17)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)AND8086/D (40.0kB)0
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Metastability and the ECLinPS FamilyAN1504/D (103.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3 V / 5 V ECL Divide by 4 DividerMC10EP33/D (186kB)11Aug, 2016
Simulation Models (3)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC100EP33D 3.3VMC100EP33D_33.IBS (5.0kB)3
IBIS Model for MC100EP33DT 3.3VMC100EP33DT_33.IBS (5.0kB)2
IBIS Model for mc100ep33dt -5.0VMC100EP33DT_-50.IBS (5.0kB)1
Package Drawings (3)
Document TitleDocument ID/SizeRevision
DFN8 2.0x2.0x0.9mm, 0.5p506AA (31.8kB)F
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100EP33DGActivePb-free Halide freeSOIC-8751-071Tube98Contact BDTIC
MC100EP33DR2GLifetimePb-free Halide freeSOIC-8751-071Tape and Reel2500
MC100EP33DTGActivePb-free Halide freeTSSOP-8948R-023Tube100Contact BDTIC
MC100EP33DTR2GActivePb-free Halide freeTSSOP-8948R-023Tape and Reel2500Contact BDTIC
MC100EP33MNR4GActivePb-free Halide freeDFN-8506AA1Tape and Reel1000Contact BDTIC
Specifications
ProductTypeInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
MC100EP33DGDividerECL CMLECL3.3 540000.38200
MC100EP33DTGDividerECL CMLECL5 3.340000.38200
MC100EP33DTR2GDividerCML ECLECL5 3.340000.38200
MC100EP33MNR4GDividerECL CMLECL3.3 540000.38200
3.3 V / 5 V ECL Divide by 4 Divider (186kB) MC10EP33
AC Characteristics of ECL Devices NB100LVEP91
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN) NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Metastability and the ECLinPS Family MC10EPT20
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for MC100EP33D 3.3V MC100EP33
IBIS Model for MC100EP33DT 3.3V MC100EP33
IBIS Model for mc100ep33dt -5.0V MC100EP33
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
DFN8 2.0x2.0x0.9mm, 0.5p NUF4220