MC100EP52: ECL Differential Clock/Data D Flip-Flop

The MC10EP/100EP52 is a differential data, differential clock D flip-flop with reset. The device is functionally equivalent to the EL52 device. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP52 allow the device to also be used as a negative edge triggered device. The EP52 employs input clamping circuitry so that under open input conditions (pulled down to VEE ) the outputs of the device will remain stable.

Features
  • 330ps Typical Propagation Delay
  • Maximum Frequency > 4 GHz Typical
  • PECL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode: VCC = 0 V with VEE = -3.0 V to -5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • Q Output will default LOW with inputs open or at VEE
  • Pb-Free Packages are Available
Applications
  • Negative edge-triggering
Application Notes (16)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Metastability and the ECLinPS FamilyAN1504/D (103.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Package Drawings (3)
Document TitleDocument ID/SizeRevision
DFN8 2.0x2.0x0.9mm, 0.5p506AA (31.8kB)F
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
Simulation Models (4)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC100EP52D 3.3VMC100EP52D_33.IBS (5.0kB)1
IBIS Model for MC100EP52D at 0.0 V VCC and -5.2 V VEEMC100EP52D_-52.IBS (6.0kB)1
IBIS Model for MC100EP52DT with VEE at -5.2 VMC100EP52DT_-52.IBS (6.0kB)1
IBIS Model for mc10ep52dt 3.3VMC10EP52DT_33.IBS (5.0kB)1
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3 V / 5 V ECL Differential Data and Clock D Flip FlopMC10EP52/D (183kB)8Aug, 2016
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100EP52DGActivePb-free Halide freeSOIC-8751-071Tube98Contact BDTIC
MC100EP52DR2GActivePb-free Halide freeSOIC-8751-071Tape and Reel2500Contact BDTIC
MC100EP52DTGActivePb-free Halide freeTSSOP-8948R-023Tube100Contact BDTIC
MC100EP52DTR2GActivePb-free Halide freeTSSOP-8948R-023Tape and Reel2500Contact BDTIC
MC100EP52MNR4GActivePb-free Halide freeDFN-8506AA1Tape and Reel1000Contact BDTIC
Specifications
ProductTypeBitsInput LevelOutput LevelVCC Typ (V)tJitter Typ (ps)tpd Typ (ns)tsu Min (ns)th Min (ns)trec Typ (ns)tR & tF Max (ps)fToggle Typ (MHz)
MC100EP52DGD-Type1CML ECLECL5 3.30.20.330.0501704000
MC100EP52DR2GD-Type1CML ECLECL5 3.30.20.330.0501704000
MC100EP52DTGD-Type1ECL CMLECL3.3 50.20.330.0501704000
MC100EP52DTR2GD-Type1ECL CMLECL5 3.30.20.330.0501704000
MC100EP52MNR4GD-Type1CML ECLECL5 3.30.20.330.0501704000
3.3 V / 5 V ECL Differential Data and Clock D Flip Flop (183kB) MC10EP52
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Metastability and the ECLinPS Family MC10EPT20
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for MC100EP52D 3.3V MC100EP52
IBIS Model for MC100EP52D at 0.0 V VCC and -5.2 V VEE MC100EP52
IBIS Model for MC100EP52DT with VEE at -5.2 V MC100EP52
IBIS Model for mc10ep52dt 3.3V MC10EP52
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
DFN8 2.0x2.0x0.9mm, 0.5p NUF4220