MC100EPT23: Translator, Dual Differential LVPECL to LVTTL

The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL/LVDS/CML input levels and LVTTL/LVCMOS output levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the EPT23 makes it ideal for applications which require the translation of a clock and a data signal.The EPT23 is available in only the ECL 100K standard. Since there are no LVPECL outputs or an external VBB reference, the EPT23 does not require both ECL standard versions. The LVPECL inputs are differential. Therefore, the MC100EPT23 can accept any standard differential LVPECL input referenced from a VCC of +3.3V.

Features
  • 1.5ns Typical Propagation Delay
  • Maximum Operating Frequency > 275MHz
  • 24mA LVTTL Outputs
  • Operating Range: VCC= 3.0 V to 3.6 V with GND = 0 V
  • Open Input Default State
  • Q Output will default LOW with inputs open or at GND
  • Pb-Free Packages are Available
Application Notes (18)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)AND8086/D (40.0kB)0
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
EPT Spice Modeling KitAND8014/D (63.0kB)0
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Metastability and the ECLinPS FamilyAN1504/D (103.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3 V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS TranslatorMC100EPT23/D (157kB)19Aug, 2016
Simulation Models (4)
Document TitleDocument ID/SizeRevisionRevision Date
EPT21/23/25 ECLinPS PlusE Translator TTL output SPICE Modeling KitAND8118/D (53.0kB)0
IBIS Model for mc100ept23mn 3.3 VMC100EPT23MN_33.IBS (7.0kB)1
IBS Model for MC100EPT23D 3.3VMC100EPT23D_33.IBS (7.0kB)3
IBS Model for MC100EPT23DTMC100EPT23DT_33.IBS (7.0kB)3
Package Drawings (3)
Document TitleDocument ID/SizeRevision
DFN8 2.0x2.0x0.9mm, 0.5p506AA (31.8kB)F
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100EPT23DGActivePb-free Halide freeSOIC-8751-071Tube98Contact BDTIC
MC100EPT23DR2GActivePb-free Halide freeSOIC-8751-071Tape and Reel2500Contact BDTIC
MC100EPT23DTGActivePb-free Halide freeTSSOP-8948R-023Tube100Contact BDTIC
MC100EPT23DTR2GActivePb-free Halide freeTSSOP-8948R-023Tape and Reel2500Contact BDTIC
MC100EPT23MNR4GActivePb-free Halide freeDFN-8506AA1Tape and Reel1000Contact BDTIC
Specifications
ProductChannelsInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
MC100EPT23DG2ECL LVDS CMLTTL3.33501.5900
MC100EPT23DR2G2CML LVDS ECLTTL3.33501.5900
MC100EPT23DTG2CML ECL LVDSTTL3.33501.5900
MC100EPT23DTR2G2LVDS ECL CMLTTL3.33501.5900
MC100EPT23MNR4G2CML ECL LVDSTTL3.33501.5900
3.3 V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator (157kB) MC100EPT23
AC Characteristics of ECL Devices NB100LVEP91
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN) NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
EPT Spice Modeling Kit MC10EPT20
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Metastability and the ECLinPS Family MC10EPT20
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
EPT21/23/25 ECLinPS PlusE Translator TTL output SPICE Modeling Kit MC100EPT25
IBIS Model for mc100ept23mn 3.3 V MC100EPT23
IBS Model for MC100EPT23D 3.3V MC100EPT23
IBS Model for MC100EPT23DT MC100EPT23
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
DFN8 2.0x2.0x0.9mm, 0.5p NUF4220