MC100LVEP34: 2.5 V / 3.3 V ECL ÷2, ÷4, ÷8 Clock Generation Chip

The MC100LVEP34 is a low skew DIV2, DIV4, DIV8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.The common enable (ENbar) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input.Upon startup, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as multiple LVEP34s in a system. Single-ended CLK input operation is limited to a VCC of ≥ 3.0 V in PECL mode, or VEE ≤ -3.0 V in NECL mode.

Features
  • 35 ps Output-to-Output Skew
  • Synchronous Enable/Disable
  • Master Reset for Synchronization
  • The 100 Series Contains Temperature Compensation.
  • PECL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V
  • Open Input Default State
  • LVDS Input Compatible
Application Notes (14)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
2.5V / 3.3V ECL DIV2, DIV4, DIV8 Clock Generation ChipMC100LVEP34/D (100kB)11Apr, 2014
Simulation Models (2)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC100LVEP34D 3.3VMC100LVEP34D_33.IBS (10.0kB)1
IBIS Model for MC100LVEP34DT 3.3VMC100LVEP34DT_33.IBS (10.0kB)1
Package Drawings (2)
Document TitleDocument ID/SizeRevision
SOIC 16 LEAD751B-05 (38.2kB)K
TSSOP-16948F-01 (41.7kB)B
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100LVEP34DGActivePb-free Halide freeSOIC-16751B-051Tube48Contact BDTIC
MC100LVEP34DR2GActivePb-free Halide freeSOIC-16751B-051Tape and Reel2500Contact BDTIC
MC100LVEP34DTGActivePb-free Halide freeTSSOP-16948F-011Tube96Contact BDTIC
MC100LVEP34DTR2GActivePb-free Halide freeTSSOP-16948F-011Tape and Reel2500Contact BDTIC
Specifications
ProductTypeInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
MC100LVEP34DGDividerCML LVDS ECLECL3.3 2.528000.7200
MC100LVEP34DR2GDividerECL LVDS CMLECL3.3 2.528000.7200
MC100LVEP34DTGDividerLVDS CML ECLECL2.5 3.328000.7200
MC100LVEP34DTR2GDividerCML LVDS ECLECL2.5 3.328000.7200
2.5V / 3.3V ECL DIV2, DIV4, DIV8 Clock Generation Chip (100kB) MC100LVEP34
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for MC100LVEP34D 3.3V MC100LVEP34
IBIS Model for MC100LVEP34DT 3.3V MC100LVEP34
SOIC 16 LEAD MC14504B
TSSOP-16 MC14504B