NB100LVEP91: Translator, AnyLevel™ Positive Input to NECL Output Voltage

The NB100LVEP91 is a triple input to NECL output translator. The device accepts LVPECL, LVTTL, HSTL, CML or LVDS signals, and translates them to differential -2.5 V / -3.3 V NECL output signals.To accomplish the level translation, the LVEP91 requires three power rails. The VCC supply should be connected to the positive supply, and the VEE pin should be connected to the negative power supply. The GNDI pins are connected to the system ground plane. Both VEE and VCC should be bypassed to ground via 0.01 uF capacitors.Under open input conditions, the Dbar input will be biased at VCC/2 and the D input will be pulled to GND. This condition will force the Q output to a low, ensuring stability.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

Features
  • Typical Maximum Frequency >2 GHz
  • 430 ps Typical Propagation Delay
  • Operating Range: VCC = 2.375 V to 3.8 V; VEE = -2.375 V to -3.8 V; GNDI = 0 V
  • Q Output will default LOW with Inputs Open or at GND
  • Pb-Free Packages are Available
Benefits
  • Design Flexibility
Application Notes (12)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)AND8086/D (40.0kB)0
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
2.5 V/3.3 V Any Level Positive Input to -2.5 V/-3.3 V LVNECL Output TranslatorNB100LVEP91/D (177kB)19Aug, 2016
Simulation Models (4)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for NB100LVEP91DW at 2.5V supplyNB100LVEP91DW_25V.IBS (24.0kB)2
IBIS Model for NB100LVEP91DW at 3.3V supplyNB100LVEP91DW_33V.IBS (24.0kB)2
IBIS Model for NB100LVEP91MN at 2.5V SupplyNB100LVEP91MN_25.IBS (24.0kB)5
IBIS Model for NB100LVEP91MN at 3.3 SupplyNB100LVEP91MN_33.IBS (24.0kB)5
Package Drawings (2)
Document TitleDocument ID/SizeRevision
QFN24, 4x4, 0.5P485L-01 (60.0kB)B
SOIC-20 WB751D-05 (36.3kB)H
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
NB100LVEP91DWGActivePb-free Halide freeSOIC-20W751D-053Tube38Contact BDTIC
NB100LVEP91DWR2GActivePb-free Halide freeSOIC-20W751D-053Tape and Reel1000Contact BDTIC
NB100LVEP91MNGActivePb-free Halide freeQFN-24485L-011Tube92Contact BDTIC
NB100LVEP91MNR2GActivePb-free Halide freeQFN-24485L-011Tape and Reel3000Contact BDTIC
Specifications
ProductChannelsInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
NB100LVEP91DWG3HSTL CML LVDSECL2.5 3.325000.5250
NB100LVEP91DWR2G3CML HSTL LVDSECL3.3 2.525000.5250
NB100LVEP91MNG3HSTL LVDS CMLECL3.3 2.525000.5250
NB100LVEP91MNR2G3HSTL CML LVDSECL3.3 2.525000.5250
2.5 V/3.3 V Any Level Positive Input to -2.5 V/-3.3 V LVNECL Output Translator (177kB) NB100LVEP91
AC Characteristics of ECL Devices NB100LVEP91
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN) NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
IBIS Model for NB100LVEP91DW at 2.5V supply NB100LVEP91
IBIS Model for NB100LVEP91DW at 3.3V supply NB100LVEP91
IBIS Model for NB100LVEP91MN at 2.5V Supply NB100LVEP91
IBIS Model for NB100LVEP91MN at 3.3 Supply NB100LVEP91
SOIC-20 WB NLSX3018
QFN24, 4x4, 0.5P NCN8026