NB3L202K: 2.5V, 3.3V Differential 1:2 HCSL Fanout Buffer

The NB3L202K is a differential 1:2 Clock fanout buffer with High−speed Current Steering Logic (HCSL) outputs. Inputs can directly accept differential LVPECL, LVDS, and HCSL signals. Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels are accepted with a proper external Vth reference supply per Figures 4 and 6. The input signal will be translated to HCSL and provides two identical copies operating up to 350 MHz. The NB3L202K is optimized for ultra−low phase noise, propagation delay variation and low output–to–output skew, and is DB200H compliant. As such, system designers can take advantage of the NB3L202K’s performance to distribute low skew clocks across the backplane or the motherboard making it ideal for Clock and Data distribution applications such as PCI Express, FBDIMM, Networking, Mobile Computing, Gigabit Ethernet, etc. Output drive current is set by connecting a 475  resistor from IREF (Pin 10) to GND per Figure 11. Outputs can also interface to LVDS receivers when terminated per Figure 12.

Features
  • Maximum Input Clock Frequency > 350 MHz
  • 2.5 V ±5% / 3.3 V ±10% Supply Voltage Operation
  • 2 HCSL Outputs
  • DB200H Compliant
  • Individual OE Control Pin for Each Bank of Outputs
  • 100 ps Max Output−to−Output Skew Performance
  • 1 ns Typical Propagation Delay
  • 500 ps Typical Rise and Fall Times
  • 80 fs Maximum Additive Phase Jitter RMS
Applications
  • Mobile Computing
  • Networking
  • Gigabit Ethernet
  • FBDIMM
  • PCI Express
Application Notes (5)
Document TitleDocument ID/SizeRevisionRevision Date
Board Level Application Notes for DFN and QFN PackagesAND8211/D (175.0kB)1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)AND8086/D (40.0kB)0
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Semiconductor Package Thermal CharacterizationAND8215/D (363.0kB)0
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Package Drawings (1)
Document TitleDocument ID/SizeRevision
QFN16 3x3, 0.5P485AE (32.1kB)C
Simulation Models (1)
Document TitleDocument ID/SizeRevisionRevision Date
NB3L202K.IBSNB3L202K.IBS (53kB)0
Evaluation Board Documents (1)
Document TitleDocument ID/SizeRevisionRevision Date
NB3L202KMNGEVB Evaluation Board User's ManualEVBUM2398-D (505kB)0
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
2.5 V, 3.3 V Differential 1:2 HCSL Fanout BufferNB3L202K/D (138kB)0Apr, 2016
Evaluation/Development Tool Information
ProductStatusComplianceShort Description
NB3L202KMNGEVBActive2.5V, 3.3V Differential 1:2 HCSL Fanout Buffer Evaluation Board
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
NB3L202KMNGActivePb-free Halide freeQFN-16485AE1Tube123Contact BDTIC
NB3L202KMNTXGActivePb-free Halide freeQFN-16485AE1Tape and Reel3000Contact BDTIC
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
NB3L202KMNGBuffer11:2HCSL LVDS LVPECLHCSL3.3 2.50.046201700350
NB3L202KMNTXGBuffer11:2LVDS HCSLHCSL3.3 2.50.046201700350
2.5 V, 3.3 V Differential 1:2 HCSL Fanout Buffer (138kB) NB3L202K
Board Level Application Notes for DFN and QFN Packages NB6L56
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN) NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Semiconductor Package Thermal Characterization NGTB15N60EG
Storage and Handling of Drypack Surface Mount Device NB3U23C
NB3L202K.IBS NB3L202K
EVBUM2398-D - 505 KB NB3L202KMNGEVB
QFN16 3x3, 0.5P NLAS4783B