NB3L8533: 2.5V/3.3V Differential 2:1 MUX to 4 LVPECL Fanout Buffer

The NB3L8533 is a low skew 1:4 LVPECL Clock fanout buffer designed explicitly for low output skew applications. The NB3L8533 features a multiplexed input which can be driven by either a differential or single−ended input to allow for the distribution of a lower speed clock along with the high speed system clock. The CLK_SEL pin will select the differential clock inputs, CLK and CLKb, when LOW (or left open and pulled LOW by the internal pull−down resistor). When CLK_SEL is HIGH, the Differential PCLK and PCLKb inputs are selected. The common enable (CLK_EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input.

Features
  • CLK/CLKb can Accept LVPECL, LVDS, HCSL, STTL and HSTL
  • PCLK/PCLKb can Accept LVPECL, LVDS, CML and SSTL
  • Four Differential LVPECL Clock Outputs
  • 1.5 ns Maximum Propagation Delay
  • LVCMOS Compatible Control Inputs
  • Selectable Differential Clock Inputs
  • Synchronous Clock Enable
  • 30 ps Max. Skew Between Outputs
  • 650 MHz Maximum Clock Output Frequency
Applications
  • Backplanes
  • Computing
  • Telecom
End Products
  • Routers
  • Servers
  • Switches
Application Notes (5)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Semiconductor Package Thermal CharacterizationAND8215/D (363.0kB)0
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Package Drawings (1)
Document TitleDocument ID/SizeRevision
TSSOP-20 WB948E-02 (39.7kB)D
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
2.5V/3.3V Differential 2:1 MUX to 4 LVPECL Fanout BufferNB3L8533/D (151kB)1Dec, 2014
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
NB3L8533DTGActivePb-free Halide freeTSSOP-20948E-021Tube75Contact BDTIC
NB3L8533DTR2GActivePb-free Halide freeTSSOP-20948E-021Tape and Reel2500Contact BDTIC
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
NB3L8533DTGBuffer12:1:4HCSL HSTL CML LVPECL SSTL LVDSLVPECL3.3 2.50.0530600650
NB3L8533DTR2GBuffer12:1:4SSTL HCSL HSTL LVDS CML LVPECLLVPECL3.3 2.50.0530600650
2.5V/3.3V Differential 2:1 MUX to 4 LVPECL Fanout Buffer (151kB) NB3L8533
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Semiconductor Package Thermal Characterization NGTB15N60EG
Storage and Handling of Drypack Surface Mount Device NB3U23C
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
TSSOP-20 WB NLSX3018