NB7L32M: ÷·2 Divider with CML Output

The NB7L32M is an integrated /2 divider with differential clock inputs and asynchronous reset.Differential clock inputs incorporate internal 50 Ω termination resistors and accept LVPECL (Positive ECL), CML, or LVDS. The high frequency reset pin is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple NB7L32M's in a system.The differential 16 mA CML output provides matching internal 50 Ω termination which guarantees 400 mV output swing when externally receiver terminated 50 Ω to VCC (See Figure 16).The device is housed in a small 3x3 mm 16 pin QFN package.

Features
  • Maximum Input Clock Frequency 14 GHz Typical
  • 200 ps Max Propagation Delay
  • 30 ps Typical Rise and Fall Times
  • < 0.5 ps Maximum (RMS) Random Clock Jitter
  • Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
  • CML Output Level (400 mV Peak-to-Peak Output), Differential Output Only
  • 50 Ω Internal Input and Output Termination Resistors
  • Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG Devices
  • Full RoHS Compliance.
Applications
  • High frequency clock division in Automated Test Equipment.
  • Ultra precise clock division in networking and telecomm applications.
Application Notes (5)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)AND8086/D (40.0kB)0
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
GigaComm (SiGe) SPICE Modeling KitAND8077/D (157kB)6
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Package Drawings (1)
Document TitleDocument ID/SizeRevision
QFN16, 3x3, 0.5P485G-01 (57.3kB)F
Simulation Models (1)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for NB7L32MNB7L32M.IBS (24.0kB)3
Evaluation Board Documents (1)
Document TitleDocument ID/SizeRevisionRevision Date
NB7L32MMNGEVB ManualEVBUM2086/D (156.0kB)1
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
2.5V/3.3V, 14GHz ÷2 Clock Divider w/CML Output and Internal TerminationNB7L32M/D (183.0kB)3
Evaluation/Development Tool Information
ProductStatusComplianceShort Description
NB7L32MMNGEVBActivePb-free2.5V / 3.3V 12 GHz Divide by 2 with CML Output Evaluation Board
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
NB7L32MMNGActivePb-free Halide freeQFN-16485G-011Tube123Contact BDTIC
NB7L32MMNR2GActivePb-free Halide freeQFN-16485G-011Tape and Reel3000Contact BDTIC
Specifications
ProductTypeInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
NB7L32MMNGDividerCML ECL LVDSCML2.5 3.3140000.15545
NB7L32MMNR2GDividerECL LVDS CMLCML3.3 2.5140000.15545
2.5V/3.3V, 14GHz ÷2 Clock Divider w/CML Output and Internal Termination (183.0kB) NB7L32M
AC Characteristics of ECL Devices NB100LVEP91
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN) NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
GigaComm (SiGe) SPICE Modeling Kit NBSG86A
Storage and Handling of Drypack Surface Mount Device NB3U23C
IBIS Model for NB7L32M NB7L32M
EVBUM2086/D - 156 NB7L32MMNGEVB
QFN16, 3x3, 0.5P NLSF308