MC100EP90: Translator, Triple ECL Input to LVPECL / PECL Output

The MC10/100EP90 is a TRIPLE ECL TO LVPECL/PECL translator. The device receives differential LVECL or ECL signals and translates them to differential LVPECL or PECL output signals. A VBB output is provided for interfacing with single ended LVECL or ECL signals at the input. If a single ended input is to be used the VBB output should be connected to the D input. The active signal would then drive the D input. When used the VBB output should be bypassed to ground by a 0.01 F capacitor. The VBB output is designed to act as the switching reference for the EP90 under single ended input switching conditions, as a result this pin can only source/sink up to 0.5mA of current. To accomplish the level translation the EP90 requires three power rails. The VCC supply should be connected to the positive supply, and the VEE connected to the negative supply. The 100 Series contains temperature compensation.

特性
  • 260 ps Typical Propagation Delay
  • Maximum Frequency > 3 GHz Typical
  • Voltage Supplies VCC = 3.0 V to 5.5 V, VEE = -3.0 V to -5.5 V, GND = 0 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • Fully Differential Design
  • Q Output will default LOW with inputs open or at VEE
  • VBB Output
  • These are Pb-Free Devices
封装
应用注释 (15)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
Translator, Triple ECL Input to LVPECL / PECL OutputMC10EP90/D (86kB)7
仿真模型 (4)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for mc100ep90dt 3.3VCC -3.3VEEMC100EP90DT_N33_P33.IBS (6.0kB)1
IBIS Model for mc100ep90dt 3.3VCC -5.0VEEMC100EP90DT_N50_P33.IBS (6.0kB)1
IBIS Model for mc100ep90dt 5.0VCC -3.3VEEMC100EP90DT_N33_P50.IBS (6.0kB)1
IBIS Model for mc100ep90dt 5.0VCC -5.0VEEMC100EP90DT_N50_P50.IBS (6.0kB)1
封装图纸 (1)
Document TitleDocument ID/SizeRevision
TSSOP-20 WB948E-02 (39.7kB)D
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
MC100EP90DTGActivePb-free Halide freeTSSOP-20948E-021Tube75联系BDTIC
MC100EP90DTR2GActivePb-free Halide freeTSSOP-20948E-021Tape and Reel2500联系BDTIC
订购产品技术参数
ProductChannelsInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
MC100EP90DTG3ECLECL5 3.330000.26170
MC100EP90DTR2G3ECLECL3.3 530000.26170
Translator, Triple ECL Input to LVPECL / PECL Output (86kB) MC10EP90
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
IBIS Model for mc100ep90dt 3.3VCC -3.3VEE MC100EP90
IBIS Model for mc100ep90dt 3.3VCC -5.0VEE MC100EP90
IBIS Model for mc100ep90dt 5.0VCC -3.3VEE MC100EP90
IBIS Model for mc100ep90dt 5.0VCC -5.0VEE MC100EP90
TSSOP-20 WB NLSX3018