MC100EPT24: Translator, LVTTL / LVCMOS to Differential LVECL
The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL translator. Because LVECL levels and LVTTL/LVCMOS levels are used, a -3.3V, +3.3V and ground are required. The small outline 8-lead SOIC package and the single gate of the EPT24 makes it ideal for those applications where space, performance, and low power are at a premium.
特性
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应用
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封装
应用注释 (18)
数据表 (1)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| 3.3 V LVTTL/LVCMOS to Differential LVECL Translator | MC100EPT24/D (159kB) | 10 | Aug, 2016 |
仿真模型 (2)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| IBIS Model for mc100ept24dt | MC100EPT24DT.IBS (5.0kB) | 3 | |
| IBS Model For MC100EPT24D | MC100EPT24D.IBS (29.0kB) | 4 |
封装图纸 (3)
| Document Title | Document ID/Size | Revision |
|---|---|---|
| DFN8 2.0x2.0x0.9mm, 0.5p | 506AA (31.8kB) | F |
| SOIC-8 Narrow Body | 751-07 (62.6kB) | AK |
| TSSOP 8 3.0x3.0x0.95 mm | 948R-02 (77.3kB) | A |
产品订购型号
| 产品 | 状况 | Compliance | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价） | ||
|---|---|---|---|---|---|---|---|---|
| MC100EPT24DG | Active | Pb-free Halide free | SOIC-8 | 751-07 | 1 | Tube | 98 | 联系BDTIC |
| MC100EPT24DR2G | Active | Pb-free Halide free | SOIC-8 | 751-07 | 1 | Tape and Reel | 2500 | 联系BDTIC |
| MC100EPT24DTG | Active | Pb-free Halide free | TSSOP-8 | 948R-02 | 3 | Tube | 100 | 联系BDTIC |
| MC100EPT24MNR4G | Active | Pb-free Halide free | DFN-8 | 506AA | 1 | Tape and Reel | 1000 | 联系BDTIC |
订购产品技术参数
| Product | Channels | Input Level | Output Level | VCC Typ (V) | fMax Typ (MHz) | tpd Typ (ns) | tR & tF Max (ps) |
|---|---|---|---|---|---|---|---|
| MC100EPT24DG | 1 | TTL CMOS | ECL | 3.3 | 1000 | 0.53 | 170 |
| MC100EPT24DR2G | 1 | TTL CMOS | ECL | 3.3 | 1000 | 0.53 | 170 |
| MC100EPT24DTG | 1 | TTL CMOS | ECL | 3.3 | 1000 | 0.53 | 170 |
| MC100EPT24MNR4G | 1 | TTL CMOS | ECL | 3.3 | 1000 | 0.53 | 170 |
- AC Characteristics of ECL Devices NB100LVEP91
- Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
- Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
- Designing with PECL (ECL at +5.0 V) NB100LVEP91
- ECL Clock Distribution Techniques NB100LVEP91
- ECLinPS Plus™ Spice Modeling Kit MC10EPT20
- ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
- EPT Spice Modeling Kit MC10EPT20
- Interfacing Between LVDS and ECL NB100ELT23L
- Interfacing with ECLinPS NB100LVEP91
- Metastability and the ECLinPS Family MC10EPT20
- Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
- Phase Lock Loop General Operations MC10H604
- Storage and Handling of Drypack Surface Mount Device NB3U23C
- Termination of ECL Logic Devices NB100LVEP91
- The ECL Translator Guide NB100LVEP91
- Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
- Using Wire-OR Ties in ECLInPS™ Designs MC10H351
- IBIS Model for mc100ept24dt MC100EPT24
- IBS Model For MC100EPT24D MC100EPT24
- SOIC-8 Narrow Body CM1216
- TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
- DFN8 2.0x2.0x0.9mm, 0.5p NUF4220
