MC100LVEL33: 3.3 V ECL ÷·4 Divider

The MC100LVEL33 is an integrated div by 4 divider. The LVEL is functionally equivalent to the EL33 and works from a 3.3 V supply.The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple LVEL33's in a system. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

特性
  • 630ps Propagation Delay
  • 4.0 GHz Typical Maximum Frequency
  • ESD Protection: >4 KV HBM, >200 V MM
  • The 100 Series Contains Temperature Compensation
  • PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with VEE= 0 V
  • NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -3.8 V
  • Internal Input Pulldown Resistors
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
  • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
  • Transistor Count = 130 devices
  • Pb-Free Packages are Available
应用
  • Phase-Locked Loops
封装
应用注释 (15)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3 V ECL Divide by 4 DividerMC100LVEL33/D (153kB)6Jul, 2016
仿真模型 (3)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC100LVEL33D 3.3V VCCMC100LVEL33D_33.IBS (7.0kB)2
IBIS Model for mc100lvel33 VEE at -3.3 VMC100LVEL33D_-33.IBS (7.0kB)2
Low Voltage ECLinPS SPICE Modeling KitAN1560/D (88.0kB)5
封装图纸 (2)
Document TitleDocument ID/SizeRevision
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
MC100LVEL33DGActivePb-free Halide freeSOIC-8751-071Tube98联系BDTIC
MC100LVEL33DR2GActivePb-free Halide freeSOIC-8751-071Tape and Reel2500联系BDTIC
MC100LVEL33DTGActivePb-free Halide freeTSSOP-8948R-023Tube100联系BDTIC
MC100LVEL33DTR2GActivePb-free Halide freeTSSOP-8948R-023Tape and Reel2500联系BDTIC
订购产品技术参数
ProductTypeInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
MC100LVEL33DGDividerECL LVDSECL3.340000.67320
MC100LVEL33DR2GDividerECL LVDSECL3.340000.67320
MC100LVEL33DTGDividerECL LVDSECL3.340000.67320
MC100LVEL33DTR2GDividerLVDS ECLECL3.340000.67320
3.3 V ECL Divide by 4 Divider (153kB) MC100LVEL33
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for MC100LVEL33D 3.3V VCC MC100LVEL33
IBIS Model for mc100lvel33 VEE at -3.3 V MC100LVEL33
Low Voltage ECLinPS SPICE Modeling Kit MC100LVELT23
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L