MC10EP131: 3.3 V / 5.0 V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock

The MC10EP131 is a Quad Master-slaved D flip-flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables. With AC performance faster than the E131 device, the EP131 is ideal for applications requiring the fastest AC performance available.Each flip-flop may be clocked separately by holding Common Clock (CC) LOW and (CCbar) HIGH, then using the Clock Enable inputs for clocking (C0-3 and C0-3bar).Common clocking is achieved by holding the C0-3 inputs LOW and C0-3bar inputs HIGH while using the differential common clock CC to clock all four flip-flops. When left floating open, any differential input will disable operation due to input pulldown resistors forcing an output default state.Individual asynchronous resets (R0-3) and an asynchronous set (SET) are provided.Data enters the master when both CC and C0-3 are LOW, and transfers to the slave when either CC or C0-3 (or both) go HIGH.The 100 Series contains temperature compensation.

特性
  • 460ps Typical Propagation Delay
  • Maximum Frequency > 3 GHz Typical
  • Differential Individual and Common Clocks
  • Individual Asynchronous Resets
  • Asynchronous Set
  • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • Q Output will default LOW with inputs open or at VEE
  • Pb-Free Packages are Available
应用
  • High Performance Logic for test systems
封装
应用注释 (10)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3V / 5V ECL Quad D Flip Flop with Set, Reset, and Differential ClockMC10EP131/D (164.0kB)10
仿真模型 (2)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC100EP131FA VCC at 3.3 VMC100EP131FA_33.IBS (6.0kB)3
IBIS Model for mc10ep131fa VEE at -5.0 VMC10EP131FA_-50.IBS (6.0kB)1
封装图纸 (1)
Document TitleDocument ID/SizeRevision
QFN32, 5x5, 0.5P, 3.1x3.1EP488AM (57.4kB)A
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
MC10EP131FAGActivePb-free Halide freeLQFP-32联系BDTIC2Tray JEDEC250联系BDTIC
MC10EP131FAR2GLifetimePb-free Halide freeLQFP-32联系BDTIC2Tape and Reel2000
MC10EP131MNGLifetimePb-free Halide freeQFN-32488AM1Tube74
MC10EP131MNR4GLifetimePb-free Halide freeQFN-32488AM1Tape and Reel1000
订购产品技术参数
ProductTypeBitsInput LevelOutput LevelVCC Typ (V)tJitter Typ (ps)tpd Typ (ns)tsu Min (ns)th Min (ns)trec Typ (ns)tR & tF Max (ps)fToggle Typ (MHz)
MC10EP131FAGD-Type4ECL CMLECL3.3 50.20.460.120.120.212503000
3.3V / 5V ECL Quad D Flip Flop with Set, Reset, and Differential Clock (164.0kB) MC10EP131
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
IBIS Model for MC100EP131FA VCC at 3.3 V MC10EP131
IBIS Model for mc10ep131fa VEE at -5.0 V MC10EP131
QFN32, 5x5, 0.5P, 3.1x3.1EP NCN6804