NB6L295: Dual Channel Programmable Delay Line with LVPECL Output

The NB6L295 is a Dual Channel Programmable Delay Chip designed primarily for Clock or Data de-skewing and timing adjustment. The NB6L295 is versatile in that two individual variable delay channels, PD0 and PD1, can be configured in one of two operating modes, a Dual Delay or an Extended Delay. In the Dual Delay Mode, each channel has a programmable delay section which is designed using a matrix of gates and a chain of multiplexers. There is a fixed minimum delay of 3.2 ns per channel. The Extended Delay Mode amounts to the additive delay of PD0 plus PD1 and is accomplished with the Serial Data Interface MSEL bit set High. This will internally cascade the output of PD0 into the input of PD1. Therefore, the Extended Delay path starts at the IN0/IN0 inputs, flows through PD0, cascades to the PD1 and outputs through Q1/Q1. There is a fixed minimum delay of 6 ns for the Extended Delay Mode. The required delay is accomplished by programming each delay channel via a 3-pin Serial Data Interface, described in the application section. The digitally selectable delay has an increment resolution of typically 11 ps with a net programmable delay range of either 0 ns to 6 ns per channel in Dual Delay Mode; or from 0 ns to 11.2 ns for the Extended Delay Mode. The Multi-Level Inputs can be driven directly by differential LVPECL, LVDS or CML logic levels; or by single-ended LVPECL, LVCMOS or LVTTL. A single enable pin is available to control both inputs. The SDI input pins are controlled by LVCMOS or LVTTL level signals. The NB6L295 LVPECL output contains temperature compensation circuitry. This device is offered in a 4 mm x 4 mm 24-pin QFN Pb-free package. The NB6L295 is a member of the ECLinPS MAX family of high performance products.

特性
  • Linearity +/- 20ps Maximum
  • Maximum Input Clock Frequency >1.5 GHz Typical
  • Programmable Range: 0 ns to 6 ns Dual Mode; Programmable Range: 0 ns to 11
  • 11 ps Delay Increments
  • INx/INxb Inputs Accept LVPECL, LVDS Levels
  • 3-Wire Serial Data Interface (SDI)
应用
  • Automated Test Equipment (ATE)Adjustable signal path delays
应用注释 (1)
Document TitleDocument ID/SizeRevisionRevision Date
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
封装图纸 (1)
Document TitleDocument ID/SizeRevision
QFN24, 4x4, 0.5P485L-01 (60.0kB)B
仿真模型 (1)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for NB6L295MNNB6L295MN.IBS (48.0kB)3
评估板文档 (1)
Document TitleDocument ID/SizeRevisionRevision Date
NB6L295MNG / NB6L295MMNG Evaluation Board User's ManualEVBUM2082/D (564.0kB)3
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential LVPECL OutputsNB6L295/D (192.0kB)4
评估板与开发工具
产品状况Compliance简短说明
NB6L295MNGEVBActivePb-freeDual Channel Programmable Delay Evaluation Board
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
NB6L295MNGActivePb-free Halide freeQFN-24485L-011Tube92联系BDTIC
NB6L295MNTXGActivePb-free Halide freeQFN-24485L-011Tape and Reel3000联系BDTIC
订购产品技术参数
ProductInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)td(prog) Min (ns)td(prog) Max (ns)td(step) Typ (ps)tJitter Typ (ps)tR & tF Max (ps)
NB6L295MNGLVDS ECL CMLECL2.5 3.3150006.98.73170
NB6L295MNTXGLVDS ECL CMLECL3.3 2.5150006.98.73170
2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential LVPECL Outputs (192.0kB) NB6L295
Termination of ECL Logic Devices NB100LVEP91
IBIS Model for NB6L295MN NB6L295
EVBUM2082/D - 564 NB6L295MMNGEVB
QFN24, 4x4, 0.5P NCN8026