These latches are ideally suited for use as temporary storage for binary information between processing units and input/output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable (C) is high and the Q output will follow the data input as long as the enable remains high. When the enable goes low, the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the enable is permitted to go high.
The '75 and 'LS75 feature complementary Q and Q\ outputs from a 4-bit latch, and are available in various 16-pin packages. For higher component density applications, the '77 and 'LS77 4-bit latches are available in 14-pin flat packages
| SN54LS75A | |
| Voltage Nodes(V) | 5 |
| Vcc range(V) | 4.5 to 5.5 |
| Input Level | TTL |
| Output Level | TTL |
| Output Drive(mA) | |
| Output | 2S |
| No. of Bits | 4 |
| tpd max(ns) | |
| Rating | Military |
| Technology Family | LS |
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN54LS75J | ACTIVE | -55 to 125 | 3.08 | 1ku | CDIP (J) | 16 | 1 | TUBE | |
| SNJ54LS75J | ACTIVE | -55 to 125 | 3.61 | 1ku | CDIP (J) | 16 | 1 | TUBE | |
| SNJ54LS75W | ACTIVE | -55 to 125 | 13.76 | 1ku | CFP (WD) | 16 | 1 | TUBE |
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN54LS75J | TBD | A42 | N/A for Pkg Type | SN54LS75J | SN54LS75J |
| SNJ54LS75J | TBD | A42 | N/A for Pkg Type | SNJ54LS75J | SNJ54LS75J |
| SNJ54LS75W | TBD | A42 | N/A for Pkg Type | SNJ54LS75W | SNJ54LS75W |
